dc0e258fe4
Previously, registers and subregisters mapped to the same Dwarf encoding. We don't really have any way to refer to subregisters directly from Dwarf, the expression emitter should instead use DW_OPs to stencil out the subregister from the whole register. This was also confusing tools that need to map back to the llvm reg (e.g. dwarfdump), since getLLVMRegNum() would arbitrarily return the _LO16 register.
88 lines
3.5 KiB
C++
88 lines
3.5 KiB
C++
//===- llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp ------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPUUnitTests.h"
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#include "gtest/gtest.h"
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using namespace llvm;
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TEST(AMDGPU, TestWave64DwarfRegMapping) {
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for (auto Triple :
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{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
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auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize64");
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if (TM) {
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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auto MRI = ST.getRegisterInfo();
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if (MRI) {
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// Wave64 Dwarf register mapping test numbers
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// PC_64 => 16, EXEC_MASK_64 => 17, S0 => 32, S63 => 95,
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// S64 => 1088, S105 => 1129, V0 => 2560, V255 => 2815,
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// A0 => 3072, A255 => 3327
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for (int DwarfEncoding :
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{16, 17, 32, 95, 1088, 1129, 2560, 2815, 3072, 3327}) {
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MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);
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EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));
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EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));
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}
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// We should get the correct LLVM register when round tripping through
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// the dwarf encoding.
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for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) {
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int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false);
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EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false));
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}
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// Verify that subregisters have no dwarf encoding.
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for (MCRegister LLSubReg :
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{AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {
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EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
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}
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}
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}
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}
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}
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TEST(AMDGPU, TestWave32DwarfRegMapping) {
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for (auto Triple :
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{"amdgcn-amd-", "amdgcn-amd-amdhsa", "amdgcn-amd-amdpal"}) {
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auto TM = createAMDGPUTargetMachine(Triple, "gfx1010", "+wavefrontsize32");
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if (TM) {
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GCNSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
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std::string(TM->getTargetFeatureString()), *TM);
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auto MRI = ST.getRegisterInfo();
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if (MRI) {
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// Wave32 Dwarf register mapping test numbers
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// PC_64 => 16, EXEC_MASK_32 => 1, S0 => 32, S63 => 95,
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// S64 => 1088, S105 => 1129, V0 => 1536, V255 => 1791,
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// A0 => 2048, A255 => 2303
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for (int DwarfEncoding :
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{16, 1, 32, 95, 1088, 1129, 1536, 1791, 2048, 2303}) {
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MCRegister Reg = *MRI->getLLVMRegNum(DwarfEncoding, false);
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EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, false));
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EXPECT_EQ(DwarfEncoding, MRI->getDwarfRegNum(Reg, true));
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}
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// We should get the correct LLVM register when round tripping through
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// the dwarf encoding.
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for (MCRegister LLReg : {AMDGPU::VGPR1, AMDGPU::AGPR2, AMDGPU::SGPR3}) {
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int DwarfEncoding = MRI->getDwarfRegNum(LLReg, false);
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EXPECT_EQ(LLReg, MRI->getLLVMRegNum(DwarfEncoding, false));
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}
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// Verify that subregisters have no dwarf encoding.
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for (MCRegister LLSubReg :
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{AMDGPU::VGPR1_LO16, AMDGPU::AGPR1_HI16, AMDGPU::SGPR1_HI16}) {
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EXPECT_EQ(MRI->getDwarfRegNum(LLSubReg, false), -1);
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}
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}
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}
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}
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}
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