62fe3dcf98
This commit adds the isnan intrinsic and provides a default expansion for it in the SDAG. However, it makes the assumption that types it operates on are IEEE-compliant types. This is not always the case. An example of that is PPC "double double" which has a representation that - Does not need to conform to IEEE requirements for isnan as it is not an IEEE-compliant type - Does not have a representation that allows for straightforward reinterpreting as an integer and use of integer operations The result was that this commit broke __builtin_isnan for ppc_fp128 making many valid numeric values report a NaN. This patch simply changes the expansion to always expand to unordered comparison (regardless of whether FP exceptions are tracked). This is inline with previous semantics.
488 lines
14 KiB
LLVM
488 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
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define i1 @isnan_float(float %x) nounwind {
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; CHECK-LABEL: isnan_float:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 3, .LBB0_1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB0_1: # %entry
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; CHECK-NEXT: addi 3, 4, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i1 @llvm.isnan.f32(float %x)
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ret i1 %0
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}
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define i1 @isnan_double(double %x) nounwind {
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; CHECK-LABEL: isnan_double:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 3, .LBB1_1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB1_1: # %entry
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; CHECK-NEXT: addi 3, 4, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i1 @llvm.isnan.f64(double %x)
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ret i1 %0
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}
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define i1 @isnan_ldouble(ppc_fp128 %x) nounwind {
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; CHECK-LABEL: isnan_ldouble:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: fcmpu 1, 2, 2
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; CHECK-NEXT: crandc 20, 7, 3
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnor 20, 3, 20
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; CHECK-NEXT: bc 12, 20, .LBB2_1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB2_1: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i1 @llvm.isnan.ppcf128(ppc_fp128 %x)
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ret i1 %0
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}
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define i1 @isnan_float_strictfp(float %x) strictfp nounwind {
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; CHECK-LABEL: isnan_float_strictfp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -16(1)
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; CHECK-NEXT: stfs 1, 12(1)
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; CHECK-NEXT: lis 3, 32640
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; CHECK-NEXT: lwz 4, 12(1)
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; CHECK-NEXT: clrlwi 4, 4, 1
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; CHECK-NEXT: cmpw 4, 3
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 1, .LBB3_1
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; CHECK-NEXT: b .LBB3_2
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; CHECK-NEXT: .LBB3_1: # %entry
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; CHECK-NEXT: addi 3, 4, 0
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; CHECK-NEXT: .LBB3_2: # %entry
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; CHECK-NEXT: addi 1, 1, 16
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i1 @llvm.isnan.f32(float %x)
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ret i1 %0
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}
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define i1 @isnan_double_strictfp(double %x) strictfp nounwind {
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; CHECK-LABEL: isnan_double_strictfp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -16(1)
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; CHECK-NEXT: stfd 1, 8(1)
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; CHECK-NEXT: lis 3, 32752
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; CHECK-NEXT: lwz 4, 12(1)
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; CHECK-NEXT: lwz 5, 8(1)
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; CHECK-NEXT: clrlwi 4, 4, 1
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; CHECK-NEXT: cmpw 4, 3
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; CHECK-NEXT: xoris 3, 4, 32752
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; CHECK-NEXT: cmplwi 1, 3, 0
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; CHECK-NEXT: crandc 20, 1, 6
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; CHECK-NEXT: cmpwi 5, 0
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; CHECK-NEXT: crandc 21, 6, 2
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: bc 12, 20, .LBB4_1
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; CHECK-NEXT: b .LBB4_2
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; CHECK-NEXT: .LBB4_1: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: .LBB4_2: # %entry
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; CHECK-NEXT: addi 1, 1, 16
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i1 @llvm.isnan.f64(double %x)
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ret i1 %0
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}
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define i1 @isnan_ldouble_strictfp(ppc_fp128 %x) strictfp nounwind {
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; CHECK-LABEL: isnan_ldouble_strictfp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: fcmpu 1, 2, 2
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; CHECK-NEXT: crandc 20, 7, 3
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: crnor 20, 3, 20
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; CHECK-NEXT: bc 12, 20, .LBB5_1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB5_1: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call i1 @llvm.isnan.ppcf128(ppc_fp128 %x)
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ret i1 %0
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}
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define <1 x i1> @isnan_float_vec1(<1 x float> %x) nounwind {
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; CHECK-LABEL: isnan_float_vec1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 3, .LBB6_1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB6_1: # %entry
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; CHECK-NEXT: addi 3, 4, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <1 x i1> @llvm.isnan.v1f32(<1 x float> %x)
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ret <1 x i1> %0
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}
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define <1 x i1> @isnan_double_vec1(<1 x double> %x) nounwind {
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; CHECK-LABEL: isnan_double_vec1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: fcmpu 0, 1, 1
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 3, .LBB7_1
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB7_1: # %entry
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; CHECK-NEXT: addi 3, 4, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <1 x i1> @llvm.isnan.v1f64(<1 x double> %x)
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ret <1 x i1> %0
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}
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define <1 x i1> @isnan_ldouble_vec1(<1 x ppc_fp128> %x) nounwind {
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; CHECK-LABEL: isnan_ldouble_vec1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -32(1)
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; CHECK-NEXT: stfd 1, 16(1)
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; CHECK-NEXT: lis 3, 32752
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; CHECK-NEXT: lwz 4, 20(1)
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; CHECK-NEXT: stfd 2, 24(1)
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; CHECK-NEXT: lwz 5, 28(1)
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; CHECK-NEXT: cmplw 1, 4, 3
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; CHECK-NEXT: lwz 3, 24(1)
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; CHECK-NEXT: xoris 4, 4, 32752
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; CHECK-NEXT: lwz 6, 16(1)
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; CHECK-NEXT: clrlwi. 5, 5, 1
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; CHECK-NEXT: cmplwi 5, 5, 0
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; CHECK-NEXT: crandc 24, 1, 22
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; CHECK-NEXT: cmpwi 3, 0
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; CHECK-NEXT: crandc 20, 22, 2
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; CHECK-NEXT: cmpwi 6, 0
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; CHECK-NEXT: cmplwi 7, 4, 0
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; CHECK-NEXT: or 3, 3, 5
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; CHECK-NEXT: crandc 21, 5, 30
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; CHECK-NEXT: crandc 22, 30, 2
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; CHECK-NEXT: cmplwi 3, 0
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; CHECK-NEXT: cror 20, 20, 24
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; CHECK-NEXT: cror 21, 22, 21
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; CHECK-NEXT: crandc 20, 20, 2
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; CHECK-NEXT: crand 21, 2, 21
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: bc 12, 20, .LBB8_1
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; CHECK-NEXT: b .LBB8_2
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; CHECK-NEXT: .LBB8_1: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: .LBB8_2: # %entry
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; CHECK-NEXT: addi 1, 1, 32
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <1 x i1> @llvm.isnan.v1ppcf128(<1 x ppc_fp128> %x)
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ret <1 x i1> %0
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}
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define <2 x i1> @isnan_float_vec2(<2 x float> %x) nounwind {
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; CHECK-LABEL: isnan_float_vec2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: fcmpu 0, 2, 2
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; CHECK-NEXT: fcmpu 1, 1, 1
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: bc 12, 7, .LBB9_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: b .LBB9_3
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; CHECK-NEXT: .LBB9_2: # %entry
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; CHECK-NEXT: addi 3, 5, 0
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; CHECK-NEXT: .LBB9_3: # %entry
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; CHECK-NEXT: bc 12, 3, .LBB9_4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB9_4: # %entry
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; CHECK-NEXT: addi 4, 5, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <2 x i1> @llvm.isnan.v2f32(<2 x float> %x)
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ret <2 x i1> %0
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}
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define <2 x i1> @isnan_double_vec2(<2 x double> %x) nounwind {
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; CHECK-LABEL: isnan_double_vec2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: fcmpu 0, 2, 2
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; CHECK-NEXT: fcmpu 1, 1, 1
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: bc 12, 7, .LBB10_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: b .LBB10_3
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; CHECK-NEXT: .LBB10_2: # %entry
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; CHECK-NEXT: addi 3, 5, 0
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; CHECK-NEXT: .LBB10_3: # %entry
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; CHECK-NEXT: bc 12, 3, .LBB10_4
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB10_4: # %entry
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; CHECK-NEXT: addi 4, 5, 0
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <2 x i1> @llvm.isnan.v2f64(<2 x double> %x)
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ret <2 x i1> %0
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}
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define <2 x i1> @isnan_ldouble_vec2(<2 x ppc_fp128> %x) nounwind {
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; CHECK-LABEL: isnan_ldouble_vec2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -48(1)
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; CHECK-NEXT: stfd 3, 32(1)
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; CHECK-NEXT: lis 3, 32752
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; CHECK-NEXT: lwz 8, 32(1)
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; CHECK-NEXT: stfd 4, 40(1)
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; CHECK-NEXT: lwz 9, 44(1)
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; CHECK-NEXT: cmpwi 1, 8, 0
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; CHECK-NEXT: lwz 10, 36(1)
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; CHECK-NEXT: lwz 8, 40(1)
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; CHECK-NEXT: clrlwi. 9, 9, 1
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; CHECK-NEXT: stfd 1, 16(1)
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; CHECK-NEXT: cmplwi 5, 9, 0
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; CHECK-NEXT: lwz 5, 20(1)
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; CHECK-NEXT: crandc 24, 1, 22
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; CHECK-NEXT: stfd 2, 24(1)
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; CHECK-NEXT: cmpwi 8, 0
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; CHECK-NEXT: lwz 4, 16(1)
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; CHECK-NEXT: cmplw 7, 10, 3
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; CHECK-NEXT: lwz 7, 28(1)
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; CHECK-NEXT: xoris 10, 10, 32752
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; CHECK-NEXT: crandc 20, 22, 2
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; CHECK-NEXT: cmplwi 10, 0
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; CHECK-NEXT: lwz 6, 24(1)
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; CHECK-NEXT: crandc 21, 29, 2
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; CHECK-NEXT: cmplw 7, 5, 3
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; CHECK-NEXT: xoris 3, 5, 32752
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; CHECK-NEXT: crandc 22, 2, 6
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; CHECK-NEXT: cmplwi 3, 0
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; CHECK-NEXT: cmpwi 1, 4, 0
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; CHECK-NEXT: crandc 23, 29, 2
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; CHECK-NEXT: crandc 25, 2, 6
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; CHECK-NEXT: clrlwi. 3, 7, 1
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; CHECK-NEXT: cmplwi 1, 3, 0
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; CHECK-NEXT: crandc 26, 1, 6
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; CHECK-NEXT: cmpwi 6, 0
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; CHECK-NEXT: or 4, 8, 9
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; CHECK-NEXT: crandc 27, 6, 2
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; CHECK-NEXT: cmplwi 4, 0
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; CHECK-NEXT: or 3, 6, 3
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; CHECK-NEXT: cror 20, 20, 24
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; CHECK-NEXT: cror 21, 22, 21
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; CHECK-NEXT: cmplwi 1, 3, 0
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; CHECK-NEXT: cror 22, 25, 23
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; CHECK-NEXT: crandc 20, 20, 2
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; CHECK-NEXT: crand 21, 2, 21
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; CHECK-NEXT: cror 23, 27, 26
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; CHECK-NEXT: crand 22, 6, 22
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: crandc 21, 23, 6
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; CHECK-NEXT: crnor 21, 22, 21
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 21, .LBB11_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: b .LBB11_3
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; CHECK-NEXT: .LBB11_2: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: .LBB11_3: # %entry
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; CHECK-NEXT: bc 12, 20, .LBB11_4
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; CHECK-NEXT: b .LBB11_5
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; CHECK-NEXT: .LBB11_4: # %entry
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: .LBB11_5: # %entry
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <2 x i1> @llvm.isnan.v2ppcf128(<2 x ppc_fp128> %x)
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ret <2 x i1> %0
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}
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define <2 x i1> @isnan_float_vec2_strictfp(<2 x float> %x) strictfp nounwind {
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; CHECK-LABEL: isnan_float_vec2_strictfp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -16(1)
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; CHECK-NEXT: stfs 1, 8(1)
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; CHECK-NEXT: lis 3, 32640
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; CHECK-NEXT: stfs 2, 12(1)
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; CHECK-NEXT: lwz 4, 12(1)
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; CHECK-NEXT: lwz 5, 8(1)
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; CHECK-NEXT: clrlwi 4, 4, 1
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; CHECK-NEXT: cmpw 4, 3
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; CHECK-NEXT: clrlwi 5, 5, 1
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: cmpw 1, 5, 3
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; CHECK-NEXT: li 5, 1
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; CHECK-NEXT: bc 12, 5, .LBB12_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: b .LBB12_3
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; CHECK-NEXT: .LBB12_2: # %entry
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; CHECK-NEXT: addi 3, 5, 0
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; CHECK-NEXT: .LBB12_3: # %entry
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; CHECK-NEXT: bc 12, 1, .LBB12_4
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; CHECK-NEXT: b .LBB12_5
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; CHECK-NEXT: .LBB12_4: # %entry
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; CHECK-NEXT: addi 4, 5, 0
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; CHECK-NEXT: .LBB12_5: # %entry
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; CHECK-NEXT: addi 1, 1, 16
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <2 x i1> @llvm.isnan.v2f32(<2 x float> %x)
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ret <2 x i1> %0
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}
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define <2 x i1> @isnan_double_vec2_strictfp(<2 x double> %x) strictfp nounwind {
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; CHECK-LABEL: isnan_double_vec2_strictfp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -32(1)
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; CHECK-NEXT: stfd 2, 24(1)
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; CHECK-NEXT: lis 3, 32752
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; CHECK-NEXT: lwz 5, 28(1)
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; CHECK-NEXT: stfd 1, 16(1)
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; CHECK-NEXT: lwz 6, 20(1)
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; CHECK-NEXT: clrlwi 5, 5, 1
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; CHECK-NEXT: lwz 7, 24(1)
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; CHECK-NEXT: cmpw 5, 3
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; CHECK-NEXT: xoris 5, 5, 32752
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; CHECK-NEXT: lwz 4, 16(1)
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; CHECK-NEXT: cmplwi 1, 5, 0
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; CHECK-NEXT: crandc 20, 1, 6
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; CHECK-NEXT: cmpwi 7, 0
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; CHECK-NEXT: clrlwi 5, 6, 1
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; CHECK-NEXT: crandc 21, 6, 2
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; CHECK-NEXT: cmpw 5, 3
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; CHECK-NEXT: xoris 3, 5, 32752
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; CHECK-NEXT: cmplwi 1, 3, 0
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; CHECK-NEXT: crandc 22, 1, 6
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; CHECK-NEXT: cmpwi 4, 0
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; CHECK-NEXT: crandc 23, 6, 2
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: crnor 21, 23, 22
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 21, .LBB13_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: b .LBB13_3
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; CHECK-NEXT: .LBB13_2: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: .LBB13_3: # %entry
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; CHECK-NEXT: bc 12, 20, .LBB13_4
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; CHECK-NEXT: b .LBB13_5
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; CHECK-NEXT: .LBB13_4: # %entry
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: .LBB13_5: # %entry
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; CHECK-NEXT: addi 1, 1, 32
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <2 x i1> @llvm.isnan.v2f64(<2 x double> %x)
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ret <2 x i1> %0
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}
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define <2 x i1> @isnan_ldouble_vec2_strictfp(<2 x ppc_fp128> %x) strictfp nounwind {
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; CHECK-LABEL: isnan_ldouble_vec2_strictfp:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stwu 1, -48(1)
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; CHECK-NEXT: stfd 3, 32(1)
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; CHECK-NEXT: lis 3, 32752
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; CHECK-NEXT: lwz 8, 32(1)
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; CHECK-NEXT: stfd 4, 40(1)
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; CHECK-NEXT: lwz 9, 44(1)
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; CHECK-NEXT: cmpwi 1, 8, 0
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; CHECK-NEXT: lwz 10, 36(1)
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; CHECK-NEXT: lwz 8, 40(1)
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; CHECK-NEXT: clrlwi. 9, 9, 1
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; CHECK-NEXT: stfd 1, 16(1)
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; CHECK-NEXT: cmplwi 5, 9, 0
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; CHECK-NEXT: lwz 5, 20(1)
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; CHECK-NEXT: crandc 24, 1, 22
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; CHECK-NEXT: stfd 2, 24(1)
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; CHECK-NEXT: cmpwi 8, 0
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; CHECK-NEXT: lwz 4, 16(1)
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; CHECK-NEXT: cmplw 7, 10, 3
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; CHECK-NEXT: lwz 7, 28(1)
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; CHECK-NEXT: xoris 10, 10, 32752
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; CHECK-NEXT: crandc 20, 22, 2
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; CHECK-NEXT: cmplwi 10, 0
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; CHECK-NEXT: lwz 6, 24(1)
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; CHECK-NEXT: crandc 21, 29, 2
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; CHECK-NEXT: cmplw 7, 5, 3
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; CHECK-NEXT: xoris 3, 5, 32752
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; CHECK-NEXT: crandc 22, 2, 6
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; CHECK-NEXT: cmplwi 3, 0
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; CHECK-NEXT: cmpwi 1, 4, 0
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; CHECK-NEXT: crandc 23, 29, 2
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; CHECK-NEXT: crandc 25, 2, 6
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; CHECK-NEXT: clrlwi. 3, 7, 1
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; CHECK-NEXT: cmplwi 1, 3, 0
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; CHECK-NEXT: crandc 26, 1, 6
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; CHECK-NEXT: cmpwi 6, 0
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; CHECK-NEXT: or 4, 8, 9
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; CHECK-NEXT: crandc 27, 6, 2
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; CHECK-NEXT: cmplwi 4, 0
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; CHECK-NEXT: or 3, 6, 3
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; CHECK-NEXT: cror 20, 20, 24
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; CHECK-NEXT: cror 21, 22, 21
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; CHECK-NEXT: cmplwi 1, 3, 0
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; CHECK-NEXT: cror 22, 25, 23
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; CHECK-NEXT: crandc 20, 20, 2
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; CHECK-NEXT: crand 21, 2, 21
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; CHECK-NEXT: cror 23, 27, 26
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; CHECK-NEXT: crand 22, 6, 22
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; CHECK-NEXT: crnor 20, 21, 20
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; CHECK-NEXT: crandc 21, 23, 6
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; CHECK-NEXT: crnor 21, 22, 21
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; CHECK-NEXT: li 4, 1
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; CHECK-NEXT: bc 12, 21, .LBB14_2
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: ori 3, 4, 0
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; CHECK-NEXT: b .LBB14_3
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; CHECK-NEXT: .LBB14_2: # %entry
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; CHECK-NEXT: li 3, 0
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; CHECK-NEXT: .LBB14_3: # %entry
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; CHECK-NEXT: bc 12, 20, .LBB14_4
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; CHECK-NEXT: b .LBB14_5
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; CHECK-NEXT: .LBB14_4: # %entry
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: .LBB14_5: # %entry
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; CHECK-NEXT: addi 1, 1, 48
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; CHECK-NEXT: blr
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entry:
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%0 = tail call <2 x i1> @llvm.isnan.v2ppcf128(<2 x ppc_fp128> %x)
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ret <2 x i1> %0
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}
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declare i1 @llvm.isnan.f32(float)
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declare i1 @llvm.isnan.f64(double)
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declare i1 @llvm.isnan.ppcf128(ppc_fp128)
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declare <1 x i1> @llvm.isnan.v1f32(<1 x float>)
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declare <1 x i1> @llvm.isnan.v1f64(<1 x double>)
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declare <1 x i1> @llvm.isnan.v1ppcf128(<1 x ppc_fp128>)
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declare <2 x i1> @llvm.isnan.v2f32(<2 x float>)
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declare <2 x i1> @llvm.isnan.v2f64(<2 x double>)
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declare <2 x i1> @llvm.isnan.v2ppcf128(<2 x ppc_fp128>)
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