65c4d6191f
At the moment, the primary induction variable for the vector loop is
created as part of the skeleton creation. This is tied to creating the
vector loop latch outside of VPlan. This prevents from modeling the
*whole* vector loop in VPlan, which in turn is required to model
preheader and exit blocks in VPlan as well.
This patch introduces a new recipe VPCanonicalIVPHIRecipe to represent the
primary IV in VPlan and CanonicalIVIncrement{NUW} opcodes for
VPInstruction to model the increment.
This allows us to partly retire createInductionVariable. At the moment,
a bit of patching up is done after executing all blocks in the plan.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D113223
64 lines
2.2 KiB
LLVM
64 lines
2.2 KiB
LLVM
; RUN: opt -loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S < %s 2>&1 | FileCheck %s
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; RUN: opt -passes='loop-vectorize' -force-vector-width=4 -force-vector-interleave=1 -S < %s 2>&1 | FileCheck %s
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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; Make sure the selects generated from reduction are always emitted
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; in deterministic order.
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; CHECK-LABEL: @foo(
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; CHECK: vector.body:
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; CHECK: icmp ule <4 x i64>
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; CHECK-NEXT: %[[VAR1:.*]] = add <4 x i32> <i32 3, i32 3, i32 3, i32 3>, %vec.phi1
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; CHECK-NEXT: %[[VAR2:.*]] = add <4 x i32> %vec.phi, <i32 5, i32 5, i32 5, i32 5>
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; CHECK: select <4 x i1> {{.*}}, <4 x i32> %[[VAR2]], <4 x i32>
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; CHECK-NEXT: select <4 x i1> {{.*}}, <4 x i32> %[[VAR1]], <4 x i32>
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; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
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;
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define internal i64 @foo(i32* %t0) !prof !1 {
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t16:
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br label %t20
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t17: ; preds = %t20
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%t18 = phi i32 [ %t24, %t20 ]
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%t19 = phi i32 [ %t28, %t20 ]
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br label %t31
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t20: ; preds = %t20, %t16
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%t21 = phi i64 [ 0, %t16 ], [ %t29, %t20 ]
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%t22 = phi i32 [ 0, %t16 ], [ %t28, %t20 ]
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%t23 = phi i32 [ 0, %t16 ], [ %t24, %t20 ]
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%t24 = add i32 3, %t23
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%t28 = add i32 %t22, 5
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%t29 = add nuw nsw i64 %t21, 1
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%t30 = icmp eq i64 %t29, undef
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br i1 %t30, label %t17, label %t20, !prof !2
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t31:
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ret i64 undef
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}
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; Make sure we do not fail when checking for ordered reduction. This test just
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; exercises the path and bails out without performing vectorization.
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; CHECK-LABEL: quux
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; CHECK-NOT: fadd <4 x
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define void @quux() {
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bb:
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br label %header
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latch: ; preds = %header
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%tmp = phi double [ %tmp6, %header ]
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br i1 undef, label %header, label %bb2
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bb2: ; preds = %latch
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%tmp3 = phi double [ %tmp, %latch ]
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ret void
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header: ; preds = %latch, %bb
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%tmp5 = phi double [ 1.300000e+01, %bb ], [ %tmp, %latch ]
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%tmp6 = fadd double %tmp5, 1.000000e+00
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br label %latch
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}
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!1 = !{!"function_entry_count", i64 801}
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!2 = !{!"branch_weights", i32 746, i32 1}
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