Matt Arsenault
57b5966dad
DAG: Handle odd vector sizes in calling conv splitting
...
This already worked if only one register piece was used,
but didn't if a type was split into multiple, unequal
sized pieces.
Fixes not splitting 3i16/v3f16 into two registers for
AMDGPU.
This will also allow fixing the ABI for 16-bit vectors
in a future commit so that it's the same for all subtargets.
llvm-svn: 341801
2018-09-10 11:49:23 +00:00
..
2017-10-02 21:54:38 +00:00
2018-09-07 12:13:45 +00:00
2018-08-26 09:51:22 +00:00
2018-07-28 13:25:19 +00:00
2018-08-16 21:30:05 +00:00
2018-05-09 02:41:08 +00:00
2018-08-22 21:47:14 +00:00
2018-08-15 20:34:54 +00:00
2018-08-25 17:48:17 +00:00
2018-06-20 16:06:09 +00:00
2018-08-29 02:12:49 +00:00
2018-07-16 12:14:17 +00:00
2018-08-20 19:28:56 +00:00
2018-08-29 02:12:49 +00:00
2017-12-19 22:05:25 +00:00
2018-05-14 12:53:11 +00:00
2018-07-18 18:01:03 +00:00
2018-08-14 23:30:32 +00:00
2018-07-16 18:51:40 +00:00
2018-05-14 12:53:11 +00:00
2018-07-26 20:56:53 +00:00
2018-09-04 16:33:34 +00:00
2018-01-26 16:51:27 +00:00
2018-09-10 11:49:23 +00:00
2018-07-28 13:25:19 +00:00
2018-06-04 18:36:22 +00:00
2018-08-30 14:21:36 +00:00
2018-05-14 12:53:11 +00:00
2017-09-13 21:15:20 +00:00
2018-07-30 19:41:25 +00:00
2018-03-29 17:21:10 +00:00
2018-09-09 14:13:22 +00:00