Carl Ritson f8816c7400 [AMDGPU] Add v5f32/VReg_160 support for MIMG instructions
Avoid having to round up to v8f32/VReg_256 when only 5 VGPRs are
required for a MIMG address operand.

Maintain _V8 instruction variants of pseudo instructions allowing
assembly prior to GFX10 to work as-is.  Currently the validator
can tell for GFX10 what the correct size is, so will disallow
oversize address registers.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D103672
2021-06-08 11:11:40 +09:00
..
2021-02-17 16:01:32 -08:00
2019-06-20 15:08:34 +00:00
2019-05-08 22:09:57 +00:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2021-02-17 16:01:32 -08:00
2019-03-19 15:50:24 +00:00
2019-07-01 17:17:45 +00:00
2021-02-17 16:01:32 -08:00
2020-09-14 13:40:17 +01:00
2019-03-12 21:02:54 +00:00
2021-02-17 16:01:32 -08:00
2021-02-17 16:01:32 -08:00
2020-08-05 12:36:26 -07:00
2020-08-05 12:36:26 -07:00
2020-06-15 16:18:05 -07:00
2019-03-19 15:50:24 +00:00
2019-04-26 16:37:51 +00:00
2021-02-17 16:01:32 -08:00
2019-03-19 15:50:24 +00:00
2020-06-15 16:18:05 -07:00
2021-02-17 16:01:32 -08:00
2019-05-08 22:09:57 +00:00
2019-05-03 15:37:07 +00:00
2021-01-21 10:51:36 -05:00
2021-02-17 16:01:32 -08:00
2020-08-09 20:50:30 +02:00
2020-06-25 10:38:23 +02:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2021-02-17 16:01:32 -08:00
2019-06-20 15:08:34 +00:00
2019-05-03 15:37:07 +00:00
2021-02-17 16:01:32 -08:00
2020-04-03 10:07:21 +01:00
2020-08-09 20:50:30 +02:00
2020-06-15 16:18:05 -07:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2020-08-09 20:50:30 +02:00
2021-03-15 21:44:15 +09:00
2020-01-12 22:44:51 -05:00

+==============================================================================+
| How to organize the lit tests                                                |
+==============================================================================+

- If you write a test for matching a single DAG opcode or intrinsic, it should
  go in a file called {opcode_name,intrinsic_name}.ll (e.g. fadd.ll)

- If you write a test that matches several DAG opcodes and checks for a single
  ISA instruction, then that test should go in a file called {ISA_name}.ll (e.g.
  bfi_int.ll

- For all other tests, use your best judgement for organizing tests and naming
  the files.

+==============================================================================+
| Naming conventions                                                           |
+==============================================================================+

- Use dash '-' and not underscore '_' to separate words in file names, unless
  the file is named after a DAG opcode or ISA instruction that has an
  underscore '_' in its name.