Simon Moll 7a86645611 [VE] VP intrinsics are legal

2021-04-30 15:47:55 +02:00

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AsmParser

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Disassembler

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MCTargetDesc

[VE] Add include for formatted_raw_ostream after 046cfb856517c6140d5e1c0989232e26d00b05b2

2021-01-29 11:18:30 -08:00

TargetInfo

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CMakeLists.txt

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LVLGen.cpp

[VE] Correct LVLGen (LVL instruction insert pass)

2020-12-09 06:33:53 +09:00

VE.h

[VE] Change inetger constants 32-bit friendly

2021-02-01 19:00:47 +09:00

VE.td

[VE] Change default CPU name to "generic"

2021-01-04 20:09:57 +09:00

VEAsmPrinter.cpp

[VE][NFC] Update comments to match the generated instructions

2021-01-07 15:13:24 +09:00

VECallingConv.td

[VE] Correct VMP allocation in calling conv

2020-12-21 22:42:24 +09:00

VEFrameLowering.cpp

[NFC][CodeGen] Tidy up TargetRegisterInfo stack realignment functions

2021-03-30 17:31:39 +01:00

VEFrameLowering.h

[VE] Optimize prologue/epilogue instructions

2020-11-30 22:22:33 +09:00

VEInstrBuilder.h

[VE] Support SJLJ exception related instructions

2021-01-05 20:19:15 +09:00

VEInstrFormats.td

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VEInstrInfo.cpp

[VE] Support copy of vector mask registers

2020-12-19 09:16:43 +09:00

VEInstrInfo.h

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VEInstrInfo.td

[VE] Fix types of multiclass template arguments in TableGen files

2021-03-20 10:36:51 -07:00

VEInstrIntrinsicVL.gen.td

[VE] Add logical mask intrinsic instructions

2020-12-15 01:34:31 +09:00

VEInstrIntrinsicVL.td

[VE] Support additional VMRGW and VMV intrinsic instructions

2021-01-11 20:50:31 +09:00

VEInstrPatternsVec.td

[VE] Fix types of multiclass template arguments in TableGen files

2021-03-20 10:36:51 -07:00

VEInstrVec.td

[VE] Add logical mask intrinsic instructions

2020-12-15 01:34:31 +09:00

VEISelDAGToDAG.cpp

[llvm] Use isa instead of dyn_cast (NFC)

2021-01-29 23:23:37 -08:00

VEISelLowering.cpp

[VE] Fix allowsMisalignedMemoryAccesses after D96097

2021-02-04 20:46:18 -08:00

VEISelLowering.h

[VE] Fix allowsMisalignedMemoryAccesses after D96097

2021-02-04 20:46:18 -08:00

VEMachineFunctionInfo.cpp

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VEMachineFunctionInfo.h

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VEMCInstLower.cpp

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VERegisterInfo.cpp

[VE] Support atomic exchange instructions

2020-12-15 17:43:11 +09:00

VERegisterInfo.h

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VERegisterInfo.td

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VESubtarget.cpp

[VE] Change default CPU name to "generic"

2021-01-04 20:09:57 +09:00

VESubtarget.h

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VETargetMachine.cpp

[llvm] Use Optional::getValueOr (NFC)

2021-01-12 21:43:50 -08:00

VETargetMachine.h

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VETargetTransformInfo.h

[VE] VP intrinsics are legal

2021-04-30 15:47:55 +02:00

VVPInstrInfo.td

[VE] Vector 'and' isel and tests

2020-12-23 13:29:29 +01:00

VVPInstrPatternsVec.td

[VE] Vector 'and' isel and tests

2020-12-23 13:29:29 +01:00

VVPNodes.def

[VP] ISD helper functions [VE] isel for vp_add, vp_and

2021-01-08 14:29:45 +01:00