0e3d38937e
It does not work because of emergency stack slots. This pass was supposed to eliminate dummy registers for the spill instructions, but the register scavenger can introduce more during PrologEpilogInserter, so some would end up left behind if they were needed. The potential for spilling the scratch resource descriptor and offset register makes doing something like this overly complicated. Reserve registers to use for the resource descriptor and use them directly in eliminateFrameIndex. Also removes creating another scratch resource descriptor when directly selecting scratch MUBUF instructions. The choice of which registers are reserved is temporary. For now it attempts to pick the next available registers after the user and system SGPRs. llvm-svn: 254329
156 lines
4.9 KiB
C++
156 lines
4.9 KiB
C++
//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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/// \file
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_AMDGPU_H
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#define LLVM_LIB_TARGET_R600_AMDGPU_H
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class AMDGPUInstrPrinter;
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class AMDGPUSubtarget;
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class AMDGPUTargetMachine;
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class FunctionPass;
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class MCAsmInfo;
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class raw_ostream;
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class Target;
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class TargetMachine;
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// R600 Passes
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FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
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FunctionPass *createR600TextureIntrinsicsReplacer();
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FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
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FunctionPass *createR600EmitClauseMarkers();
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FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
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FunctionPass *createR600Packetizer(TargetMachine &tm);
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FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
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FunctionPass *createAMDGPUCFGStructurizerPass();
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// SI Passes
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FunctionPass *createSITypeRewriter();
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FunctionPass *createSIAnnotateControlFlowPass();
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FunctionPass *createSIFoldOperandsPass();
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FunctionPass *createSILowerI1CopiesPass();
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FunctionPass *createSIShrinkInstructionsPass();
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FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
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FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
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FunctionPass *createSIFixControlFlowLiveIntervalsPass();
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FunctionPass *createSIFixSGPRCopiesPass();
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FunctionPass *createSIFixSGPRLiveRangesPass();
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FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
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FunctionPass *createSIInsertWaits(TargetMachine &tm);
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ModulePass *createAMDGPUAnnotateKernelFeaturesPass();
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void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
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extern char &AMDGPUAnnotateKernelFeaturesID;
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void initializeSIFoldOperandsPass(PassRegistry &);
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extern char &SIFoldOperandsID;
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void initializeSIFixSGPRCopiesPass(PassRegistry &);
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extern char &SIFixSGPRCopiesID;
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void initializeSILowerI1CopiesPass(PassRegistry &);
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extern char &SILowerI1CopiesID;
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void initializeSILoadStoreOptimizerPass(PassRegistry &);
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extern char &SILoadStoreOptimizerID;
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// Passes common to R600 and SI
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FunctionPass *createAMDGPUPromoteAlloca(const AMDGPUSubtarget &ST);
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Pass *createAMDGPUStructurizeCFGPass();
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FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
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ModulePass *createAMDGPUAlwaysInlinePass();
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ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
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void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
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extern char &SIFixControlFlowLiveIntervalsID;
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void initializeSIFixSGPRLiveRangesPass(PassRegistry&);
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extern char &SIFixSGPRLiveRangesID;
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extern Target TheAMDGPUTarget;
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extern Target TheGCNTarget;
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namespace AMDGPU {
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enum TargetIndex {
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TI_CONSTDATA_START,
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TI_SCRATCH_RSRC_DWORD0,
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TI_SCRATCH_RSRC_DWORD1,
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TI_SCRATCH_RSRC_DWORD2,
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TI_SCRATCH_RSRC_DWORD3
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};
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}
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#define END_OF_TEXT_LABEL_NAME "EndOfTextLabel"
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} // End namespace llvm
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namespace ShaderType {
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enum Type {
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PIXEL = 0,
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VERTEX = 1,
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GEOMETRY = 2,
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COMPUTE = 3
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};
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}
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/// OpenCL uses address spaces to differentiate between
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/// various memory regions on the hardware. On the CPU
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/// all of the address spaces point to the same memory,
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/// however on the GPU, each address space points to
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/// a separate piece of memory that is unique from other
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/// memory locations.
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namespace AMDGPUAS {
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enum AddressSpaces : unsigned {
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PRIVATE_ADDRESS = 0, ///< Address space for private memory.
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GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
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CONSTANT_ADDRESS = 2, ///< Address space for constant memory
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LOCAL_ADDRESS = 3, ///< Address space for local memory.
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FLAT_ADDRESS = 4, ///< Address space for flat memory.
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REGION_ADDRESS = 5, ///< Address space for region memory.
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PARAM_D_ADDRESS = 6, ///< Address space for direct addressible parameter memory (CONST0)
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PARAM_I_ADDRESS = 7, ///< Address space for indirect addressible parameter memory (VTX1)
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// Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
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// order to be able to dynamically index a constant buffer, for example:
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//
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// ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
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CONSTANT_BUFFER_0 = 8,
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CONSTANT_BUFFER_1 = 9,
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CONSTANT_BUFFER_2 = 10,
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CONSTANT_BUFFER_3 = 11,
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CONSTANT_BUFFER_4 = 12,
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CONSTANT_BUFFER_5 = 13,
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CONSTANT_BUFFER_6 = 14,
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CONSTANT_BUFFER_7 = 15,
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CONSTANT_BUFFER_8 = 16,
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CONSTANT_BUFFER_9 = 17,
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CONSTANT_BUFFER_10 = 18,
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CONSTANT_BUFFER_11 = 19,
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CONSTANT_BUFFER_12 = 20,
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CONSTANT_BUFFER_13 = 21,
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CONSTANT_BUFFER_14 = 22,
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CONSTANT_BUFFER_15 = 23,
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ADDRESS_NONE = 24, ///< Address space for unknown memory.
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LAST_ADDRESS = ADDRESS_NONE,
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// Some places use this if the address space can't be determined.
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UNKNOWN_ADDRESS_SPACE = ~0u
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};
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} // namespace AMDGPUAS
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#endif
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