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llvm-project/llvm/lib/Target/RISCV
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Craig Topper d9500c2e23 [RISCV] Add isel patterns for sbsetw/sbclrw/sbinvw with sext_inreg as the root. 
This handles cases were the input isn't known to be sign extended.
2020-11-26 02:03:06 -08:00
..
AsmParser
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Disassembler
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
MCTargetDesc
[AsmWriter] Factor out mnemonic generation to accessible getMnemonic.
2020-11-17 09:47:38 +00:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
Utils
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CMakeLists.txt
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
RISCV.h
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RISCV.td
[RISCV] Remove RV32 HwMode. Use DefaultMode for RV32
2020-11-20 11:16:06 -08:00
RISCVAsmPrinter.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVCallingConv.td
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RISCVCallLowering.cpp
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RISCVCallLowering.h
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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RISCVFrameLowering.cpp
[RISCV] Add GHC calling convention
2020-11-24 22:35:23 +00:00
RISCVFrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVInstrFormats.td
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RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
[RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot
2020-11-18 19:20:03 -08:00
RISCVInstrInfo.h
[RISCV] Don't include CodeGen layer files in MC layer
2020-11-12 07:45:38 -08:00
RISCVInstrInfo.td
[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
2020-11-25 21:57:48 -08:00
RISCVInstrInfoA.td
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RISCVInstrInfoB.td
[RISCV] Add isel patterns for sbsetw/sbclrw/sbinvw with sext_inreg as the root.
2020-11-26 02:03:06 -08:00
RISCVInstrInfoC.td
[RISCV] Remove unused PatFrag argument from the tablegen class used for c.beqz/c.bnez. NFC
2020-11-25 20:35:23 -08:00
RISCVInstrInfoD.td
[SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets.
2020-11-23 10:09:20 -08:00
RISCVInstrInfoF.td
[SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma and fmad nodes in tablegen. Remove explicit commuted patterns from targets.
2020-11-23 10:09:20 -08:00
RISCVInstrInfoM.td
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RISCVInstrInfoV.td
[RISCV] Use register class VR for V instruction operands directly.
2020-11-19 05:59:46 +08:00
RISCVInstructionSelector.cpp
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RISCVISelDAGToDAG.cpp
[RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.
2020-11-20 10:25:47 -08:00
RISCVISelDAGToDAG.h
[RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.
2020-11-20 10:25:47 -08:00
RISCVISelLowering.cpp
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
RISCVISelLowering.h
[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
2020-11-25 15:07:34 -08:00
RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMachineFunctionInfo.h
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
[NFC][RISCV] Simplify pass arg of RISCVMergeBaseOffsetOpt
2020-09-03 20:01:23 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Add GHC calling convention
2020-11-24 22:35:23 +00:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Remove unused VM register class
2020-11-23 14:17:06 -08:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSubtarget.h
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSystemOperands.td
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RISCVTargetMachine.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
RISCVTargetTransformInfo.h
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00