1c00d096a6
The VE backend represents vector instructions with an explicit 'i32' vector length operand. In the VE ISA, the vector length is always read from the VL hardware register. The LVLGen pass inserts 'lvl' instructions as necessary to set VL to the right value before each vector instruction. Reviewed By: kaz7 Differential Revision: https://reviews.llvm.org/D91416
124 lines
3.6 KiB
C++
124 lines
3.6 KiB
C++
//===-- VETargetMachine.cpp - Define TargetMachine for VE -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "VETargetMachine.h"
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#include "TargetInfo/VETargetInfo.h"
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#include "VE.h"
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#include "VETargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "ve"
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeVETarget() {
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// Register the target.
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RegisterTargetMachine<VETargetMachine> X(getTheVETarget());
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}
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static std::string computeDataLayout(const Triple &T) {
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// Aurora VE is little endian
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std::string Ret = "e";
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// Use ELF mangling
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Ret += "-m:e";
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// Alignments for 64 bit integers.
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Ret += "-i64:64";
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// VE supports 32 bit and 64 bits integer on registers
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Ret += "-n32:64";
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// Stack alignment is 128 bits
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Ret += "-S128";
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return Ret;
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}
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static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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if (!RM.hasValue())
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return Reloc::Static;
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return *RM;
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}
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class VEELFTargetObjectFile : public TargetLoweringObjectFileELF {
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void Initialize(MCContext &Ctx, const TargetMachine &TM) override {
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TargetLoweringObjectFileELF::Initialize(Ctx, TM);
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InitializeELF(TM.Options.UseInitArray);
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}
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};
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF() {
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return std::make_unique<VEELFTargetObjectFile>();
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}
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/// Create an Aurora VE architecture model
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VETargetMachine::VETargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Optional<Reloc::Model> RM,
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Optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
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getEffectiveRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(createTLOF()),
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Subtarget(TT, std::string(CPU), std::string(FS), *this) {
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initAsmInfo();
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}
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VETargetMachine::~VETargetMachine() {}
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TargetTransformInfo VETargetMachine::getTargetTransformInfo(const Function &F) {
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return TargetTransformInfo(VETTIImpl(this, F));
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}
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namespace {
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/// VE Code Generator Pass Configuration Options.
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class VEPassConfig : public TargetPassConfig {
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public:
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VEPassConfig(VETargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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VETargetMachine &getVETargetMachine() const {
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return getTM<VETargetMachine>();
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}
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void addIRPasses() override;
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bool addInstSelector() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *VETargetMachine::createPassConfig(PassManagerBase &PM) {
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return new VEPassConfig(*this, PM);
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}
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void VEPassConfig::addIRPasses() {
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// VE requires atomic expand pass.
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addPass(createAtomicExpandPass());
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TargetPassConfig::addIRPasses();
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}
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bool VEPassConfig::addInstSelector() {
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addPass(createVEISelDag(getVETargetMachine()));
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return false;
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}
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void VEPassConfig::addPreEmitPass() {
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// LVLGen should be called after scheduling and register allocation
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addPass(createLVLGenPass());
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}
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