46357438ba
If an AddRec is expanded outside a loop with a single exit block, check if any of the (lcssa) phi nodes in the exit block match the AddRec. If that's the case, simply use the existing lcssa phi. This can reduce the number of instruction created for SCEV expansions, mainly for runtime checks generated by the loop vectorizer. Compile-time impact should be mostly neutral https://llvm-compile-time-tracker.com/compare.php?from=48c7a3187f9831304a38df9bdb3b4d5bf6b6b1a2&to=cf9d039a7b0db5d0d912e0e2c01b19c2a653273a&stat=instructions:u PR: https://github.com/llvm/llvm-project/pull/147214
197 lines
10 KiB
LLVM
197 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -p loop-vectorize -force-vector-width=2 -S %s | FileCheck %s
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declare noalias noundef ptr @calloc(i64 noundef, i64 noundef)
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define void @reuse_lcssa_phi_for_add_rec1(ptr %head) {
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; CHECK-LABEL: define void @reuse_lcssa_phi_for_add_rec1(
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; CHECK-SAME: ptr [[HEAD:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP_1:.*]]
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; CHECK: [[LOOP_1]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 1, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[FOR:%.*]] = phi ptr [ [[HEAD]], %[[ENTRY]] ], [ [[L_1:%.*]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[L_1]] = load ptr, ptr [[FOR]], align 8
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; CHECK-NEXT: [[IV_2_NEXT]] = add nuw nsw i32 [[IV_2]], 1
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; CHECK-NEXT: [[EC_1:%.*]] = icmp eq ptr [[L_1]], null
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; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 1
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; CHECK-NEXT: br i1 [[EC_1]], label %[[PH:.*]], label %[[LOOP_1]]
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; CHECK: [[PH]]:
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; CHECK-NEXT: [[IV_LCSSA:%.*]] = phi i64 [ [[IV]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = phi i32 [ [[IV_2_NEXT]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[SRC_2:%.*]] = tail call noalias noundef dereferenceable_or_null(8) ptr @calloc(i64 1, i64 8)
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; CHECK-NEXT: [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[TMP0]], i32 1)
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; CHECK-NEXT: [[TMP1:%.*]] = sub i32 [[TMP0]], [[SMIN]]
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; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
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; CHECK-NEXT: [[TMP3:%.*]] = add nuw nsw i64 [[TMP2]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP3]], 2
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP3]], 2
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP3]], [[N_MOD_VF]]
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; CHECK-NEXT: [[TMP4:%.*]] = sub i64 [[IV_LCSSA]], [[N_VEC]]
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i64 [[IV_LCSSA]], [[INDEX]]
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr ptr, ptr [[SRC_2]], i64 [[OFFSET_IDX]]
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; CHECK-NEXT: [[TMP6:%.*]] = getelementptr ptr, ptr [[TMP5]], i32 0
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr ptr, ptr [[TMP6]], i32 -1
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x ptr>, ptr [[TMP7]], align 8
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; CHECK-NEXT: [[REVERSE:%.*]] = shufflevector <2 x ptr> [[WIDE_LOAD]], <2 x ptr> poison, <2 x i32> <i32 1, i32 0>
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; CHECK-NEXT: [[TMP8:%.*]] = extractelement <2 x ptr> [[REVERSE]], i32 0
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; CHECK-NEXT: store ptr null, ptr [[TMP8]], align 8
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; CHECK-NEXT: [[TMP9:%.*]] = extractelement <2 x ptr> [[REVERSE]], i32 1
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; CHECK-NEXT: store ptr null, ptr [[TMP9]], align 8
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP10]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP3]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_END:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP4]], %[[MIDDLE_BLOCK]] ], [ [[IV_LCSSA]], %[[PH]] ]
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; CHECK-NEXT: br label %[[LOOP_2:.*]]
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; CHECK: [[LOOP_2]]:
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; CHECK-NEXT: [[IV_3:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT_3:%.*]], %[[LOOP_2]] ]
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; CHECK-NEXT: [[IV_NEXT_3]] = add nsw i64 [[IV_3]], -1
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; CHECK-NEXT: [[GEP_SRC_2:%.*]] = getelementptr ptr, ptr [[SRC_2]], i64 [[IV_3]]
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; CHECK-NEXT: [[L:%.*]] = load ptr, ptr [[GEP_SRC_2]], align 8
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; CHECK-NEXT: store ptr null, ptr [[L]], align 8
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; CHECK-NEXT: [[T:%.*]] = trunc nuw i64 [[IV_3]] to i32
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; CHECK-NEXT: [[EC_2:%.*]] = icmp sgt i32 [[T]], 1
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; CHECK-NEXT: br i1 [[EC_2]], label %[[LOOP_2]], label %[[FOR_END]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[FOR_END]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.1
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loop.1:
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%iv = phi i64 [ 1, %entry ], [ %iv.next, %loop.1 ]
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%iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop.1 ]
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%for = phi ptr [ %head, %entry ], [ %l.1, %loop.1 ]
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%l.1 = load ptr, ptr %for, align 8
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%iv.2.next = add nuw nsw i32 %iv.2, 1
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%ec.1 = icmp eq ptr %l.1, null
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%iv.next = add nuw i64 %iv, 1
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br i1 %ec.1, label %ph, label %loop.1
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ph:
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%iv.lcssa = phi i64 [ %iv, %loop.1 ]
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%iv.2.next.lcssa = phi i32 [ %iv.2.next, %loop.1 ]
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%src.2 = tail call noalias noundef dereferenceable_or_null(8) ptr @calloc(i64 1, i64 8)
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br label %loop.2
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loop.2:
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%iv.3 = phi i64 [ %iv.lcssa, %ph ], [ %iv.next.3, %loop.2 ]
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%iv.next.3 = add nsw i64 %iv.3, -1
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%gep.src.2 = getelementptr ptr, ptr %src.2, i64 %iv.3
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%l = load ptr, ptr %gep.src.2, align 8
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store ptr null, ptr %l, align 8
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%t = trunc nuw i64 %iv.3 to i32
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%ec.2 = icmp sgt i32 %t, 1
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br i1 %ec.2, label %loop.2, label %for.end
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for.end:
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ret void
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}
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declare i32 @val()
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define void @runtime_checks_ptr_inductions(ptr %dst.1, ptr %dst.2, i1 %c) {
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; CHECK-LABEL: define void @runtime_checks_ptr_inductions(
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; CHECK-SAME: ptr [[DST_1:%.*]], ptr [[DST_2:%.*]], i1 [[C:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[DST_11:%.*]] = ptrtoint ptr [[DST_1]] to i64
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; CHECK-NEXT: br label %[[LOOP_1:.*]]
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; CHECK: [[LOOP_1]]:
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; CHECK-NEXT: [[INDVAR:%.*]] = phi i64 [ [[INDVAR_NEXT:%.*]], %[[LOOP_1]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: [[PTR_IV_1:%.*]] = phi ptr [ [[DST_1]], %[[ENTRY]] ], [ [[PTR_IV_1_NEXT:%.*]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[CALL:%.*]] = call i32 @val()
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; CHECK-NEXT: [[SEL_DST:%.*]] = select i1 [[C]], ptr [[DST_1]], ptr [[DST_2]]
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; CHECK-NEXT: [[PTR_IV_1_NEXT]] = getelementptr i8, ptr [[PTR_IV_1]], i64 1
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; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i32 [[CALL]], 0
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; CHECK-NEXT: [[INDVAR_NEXT]] = add i64 [[INDVAR]], 1
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; CHECK-NEXT: br i1 [[EC_1]], label %[[LOOP_2_HEADER_PREHEADER:.*]], label %[[LOOP_1]]
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; CHECK: [[LOOP_2_HEADER_PREHEADER]]:
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; CHECK-NEXT: [[SEL_DST_LCSSA2:%.*]] = phi ptr [ [[SEL_DST]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[INDVAR_LCSSA:%.*]] = phi i64 [ [[INDVAR]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[PTR_IV_1_LCSSA:%.*]] = phi ptr [ [[PTR_IV_1]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[SEL_DST_LCSSA:%.*]] = phi ptr [ [[SEL_DST]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[SEL_DST_LCSSA23:%.*]] = ptrtoint ptr [[SEL_DST_LCSSA2]] to i64
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
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; CHECK: [[VECTOR_MEMCHECK]]:
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDVAR_LCSSA]], [[DST_11]]
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; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[SEL_DST_LCSSA23]]
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; CHECK-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2
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; CHECK-NEXT: br i1 [[DIFF_CHECK]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[PTR_IV_1_LCSSA]], i64 1022
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[SEL_DST_LCSSA]], i64 1022
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PTR_IV_1_LCSSA]], i64 [[INDEX]]
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; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[SEL_DST_LCSSA]], i64 [[INDEX]]
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[NEXT_GEP4]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <2 x i8>, ptr [[TMP4]], align 1
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i32 0
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; CHECK-NEXT: store <2 x i8> [[WIDE_LOAD]], ptr [[TMP5]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2
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; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1022
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; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 1023, %[[MIDDLE_BLOCK]] ], [ 1, %[[LOOP_2_HEADER_PREHEADER]] ], [ 1, %[[VECTOR_MEMCHECK]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL5:%.*]] = phi ptr [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[PTR_IV_1_LCSSA]], %[[LOOP_2_HEADER_PREHEADER]] ], [ [[PTR_IV_1_LCSSA]], %[[VECTOR_MEMCHECK]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL6:%.*]] = phi ptr [ [[TMP3]], %[[MIDDLE_BLOCK]] ], [ [[SEL_DST_LCSSA]], %[[LOOP_2_HEADER_PREHEADER]] ], [ [[SEL_DST_LCSSA]], %[[VECTOR_MEMCHECK]] ]
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; CHECK-NEXT: br label %[[LOOP_2_HEADER:.*]]
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; CHECK: [[LOOP_2_HEADER]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[DEC7:%.*]], %[[LOOP_2_LATCH:.*]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[PTR_IV_2:%.*]] = phi ptr [ [[PTR_IV_2_NEXT:%.*]], %[[LOOP_2_LATCH]] ], [ [[BC_RESUME_VAL5]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[PTR_IV_3:%.*]] = phi ptr [ [[PTR_IV_3_NEXT:%.*]], %[[LOOP_2_LATCH]] ], [ [[BC_RESUME_VAL6]], %[[SCALAR_PH]] ]
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; CHECK-NEXT: [[EC_2:%.*]] = icmp eq i32 [[IV]], 1024
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; CHECK-NEXT: br i1 [[EC_2]], label %[[EXIT:.*]], label %[[LOOP_2_LATCH]]
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; CHECK: [[LOOP_2_LATCH]]:
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; CHECK-NEXT: [[DEC7]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[PTR_IV_3_NEXT]] = getelementptr i8, ptr [[PTR_IV_3]], i64 1
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; CHECK-NEXT: [[L:%.*]] = load i8, ptr [[PTR_IV_3]], align 1
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; CHECK-NEXT: [[PTR_IV_2_NEXT]] = getelementptr i8, ptr [[PTR_IV_2]], i64 1
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; CHECK-NEXT: store i8 [[L]], ptr [[PTR_IV_2]], align 1
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; CHECK-NEXT: br label %[[LOOP_2_HEADER]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.1
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loop.1:
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%ptr.iv.1 = phi ptr [ %dst.1, %entry ], [ %ptr.iv.1.next, %loop.1 ]
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%call = call i32 @val()
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%sel.dst = select i1 %c, ptr %dst.1, ptr %dst.2
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%ptr.iv.1.next = getelementptr i8, ptr %ptr.iv.1, i64 1
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%ec.1 = icmp eq i32 %call, 0
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br i1 %ec.1, label %loop.2.header, label %loop.1
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loop.2.header:
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%iv = phi i32 [ 1, %loop.1 ], [ %dec7, %loop.2.latch ]
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%ptr.iv.2 = phi ptr [ %ptr.iv.1, %loop.1 ], [ %ptr.iv.2.next, %loop.2.latch ]
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%ptr.iv.3 = phi ptr [ %sel.dst, %loop.1 ], [ %ptr.iv.3.next, %loop.2.latch ]
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%ec.2 = icmp eq i32 %iv, 1024
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br i1 %ec.2, label %exit, label %loop.2.latch
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loop.2.latch:
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%dec7 = add i32 %iv, 1
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%ptr.iv.3.next = getelementptr i8, ptr %ptr.iv.3, i64 1
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%l = load i8, ptr %ptr.iv.3, align 1
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%ptr.iv.2.next = getelementptr i8, ptr %ptr.iv.2, i64 1
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store i8 %l, ptr %ptr.iv.2, align 1
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br label %loop.2.header
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exit:
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ret void
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}
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