shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/lib/Target/AArch64
History
David Sherwood f15b6b2907 [AArch64] Add target hook for preferPredicateOverEpilogue 
This patch adds the AArch64 hook for preferPredicateOverEpilogue,
which currently returns true if SVE is enabled and one of the
following conditions (non-exhaustive) is met:

1. The "sve-tail-folding" option is set to "all", or
2. The "sve-tail-folding" option is set to "all+noreductions"
and the loop does not contain reductions,
3. The "sve-tail-folding" option is set to "all+norecurrences"
and the loop has no first-order recurrences.

Currently the default option is "disabled", but this will be
changed in a later patch.

I've added new tests to show the options behave as expected here:

  Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll

Differential Revision: https://reviews.llvm.org/D129560
2022-07-21 17:20:06 +01:00
..
AsmParser
Don't use Optional::hasValue (NFC)
2022-06-20 20:05:16 -07:00
Disassembler
[MCDisassembler] Disambiguate Size parameter in tryAddingSymbolicOperand()
2022-05-25 13:44:32 -07:00
GISel
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
MCTargetDesc
[llvm][AArch64] Add missing FPCR, H and B registers to Codeview mapping
2022-07-19 09:33:13 +00:00
TargetInfo
…
Utils
[llvm][AArch64] Fix "+all" feature for sysreg aliases
2022-07-06 08:41:53 +00:00
AArch64.h
[CodeGen] Async unwind - add a pass to fix CFI information
2022-04-11 13:27:26 +01:00
AArch64.td
[AArch64][NFC] Set true for default of subfeature is more readable
2022-07-19 09:00:00 +08:00
AArch64A53Fix835769.cpp
Fix warnings about variables that are set but only used in debug mode
2022-04-06 10:01:46 +03:00
AArch64A57FPLoadBalancing.cpp
…
AArch64AdvSIMDScalarPass.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64AsmPrinter.cpp
[CodeGen] Move instruction predicate verification to emitInstruction
2022-07-14 09:33:28 +01:00
AArch64BranchTargets.cpp
…
AArch64CallingConvention.cpp
…
AArch64CallingConvention.h
…
AArch64CallingConvention.td
[AArch64] Make nxv1i1 types a legal type for SVE.
2022-07-01 15:11:13 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
…
AArch64CollectLOH.cpp
[llvm] Call *set::insert without checking membership first (NFC)
2022-06-18 10:17:22 -07:00
AArch64Combine.td
[AArch64][GlobalISel] Add undef combines to postlegalizer combiner.
2022-05-05 09:22:08 -07:00
AArch64CompressJumpTables.cpp
…
AArch64CondBrTuning.cpp
[llvm] Use range-based for loops (NFC)
2021-11-28 10:04:54 -08:00
AArch64ConditionalCompares.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
AArch64ConditionOptimizer.cpp
…
AArch64DeadRegisterDefinitionsPass.cpp
…
AArch64ExpandImm.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AArch64ExpandImm.h
…
AArch64ExpandPseudoInsts.cpp
Reland "[llvm][AArch64] Insert "bti j" after call to setjmp"
2022-03-23 11:43:43 +00:00
AArch64FalkorHWPFFix.cpp
[Target] use getSubtarget<> instead of static_cast<>(getSubtarget())
2022-05-26 11:22:41 -07:00
AArch64FastISel.cpp
[Target] use getSubtarget<> instead of static_cast<>(getSubtarget())
2022-05-26 11:22:41 -07:00
AArch64FrameLowering.cpp
[MC] Add 'G' to augmentation string for MTE instrumented functions
2022-06-08 12:36:32 -07:00
AArch64FrameLowering.h
[AArch64] Add support for -fzero-call-used-regs
2022-05-19 16:58:28 -07:00
AArch64GenRegisterBankInfo.def
…
AArch64InstrAtomics.td
GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD
2022-07-08 11:55:08 -04:00
AArch64InstrFormats.td
[AArch64] Use SUBXrx64 for dynamic stack to refer to sp
2022-07-20 11:46:10 +08:00
AArch64InstrGISel.td
…
AArch64InstrInfo.cpp
[MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency
2022-06-28 21:42:51 +00:00
AArch64InstrInfo.h
[MachineScheduler] Order more stores by ascending address
2022-06-13 17:33:50 +08:00
AArch64InstrInfo.td
Reland "[AArch64] Add a tablegen pattern for UZP2."
2022-07-20 09:47:32 +01:00
AArch64ISelDAGToDAG.cpp
[AArch64] Use SUBXrx64 for dynamic stack to refer to sp
2022-07-20 11:46:10 +08:00
AArch64ISelLowering.cpp
[AArch64][SVE] Add DAG-Combine to push bitcasts from floating point loads after DUPLANE128
2022-07-21 11:00:10 +00:00
AArch64ISelLowering.h
[DAG] SimplifyDemandedBits - relax "xor (X >> ShiftC), XorC --> (not X) >> ShiftC" to match only demanded bits
2022-07-19 10:59:07 +01:00
AArch64LoadStoreOptimizer.cpp
[MachineScheduler] Order more stores by ascending address
2022-06-13 17:33:50 +08:00
AArch64LowerHomogeneousPrologEpilog.cpp
…
AArch64MachineFunctionInfo.cpp
[llvm] Don't use Optional::hasValue (NFC)
2022-06-20 10:38:12 -07:00
AArch64MachineFunctionInfo.h
[SVE][AArch64] Refine hasSVEArgsOrReturn
2022-07-01 13:24:55 +00:00
AArch64MachineScheduler.cpp
[AArch64][NFC] Set true for default of subfeature is more readable
2022-07-19 09:00:00 +08:00
AArch64MachineScheduler.h
[AArch64] Order STP Q's by ascending address
2022-05-23 09:50:44 +01:00
AArch64MacroFusion.cpp
[AArch64] Split fuse-literals feature
2022-04-11 05:27:11 +00:00
AArch64MacroFusion.h
…
AArch64MCInstLower.cpp
…
AArch64MCInstLower.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64MIPeepholeOpt.cpp
[llvm] Don't use Optional::getValue (NFC)
2022-06-20 22:45:45 -07:00
AArch64PBQPRegAlloc.cpp
…
AArch64PBQPRegAlloc.h
…
AArch64PerfectShuffle.h
[AArch64] Teach perfect shuffles tables about D-lane movs
2022-05-17 18:16:45 +01:00
AArch64PfmCounters.td
…
AArch64PromoteConstant.cpp
…
AArch64RedundantCopyElimination.cpp
…
AArch64RegisterBanks.td
…
AArch64RegisterInfo.cpp
[SVE][AArch64] Refine hasSVEArgsOrReturn
2022-07-01 13:24:55 +00:00
AArch64RegisterInfo.h
[SVE][AArch64] Refine hasSVEArgsOrReturn
2022-07-01 13:24:55 +00:00
AArch64RegisterInfo.td
[AArch64] Make nxv1i1 types a legal type for SVE.
2022-07-01 15:11:13 +00:00
AArch64SchedA53.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedA55.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedA57.td
[AArch64][NFC] Drop 'V' from ASIMD FP convert, other, D/Q-form regex
2022-07-14 09:32:20 +00:00
AArch64SchedA57WriteRes.td
…
AArch64SchedA64FX.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedAmpere1.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedCyclone.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedExynosM3.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedExynosM4.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedExynosM5.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedFalkor.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedFalkorDetails.td
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
AArch64SchedKryo.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedKryoDetails.td
…
AArch64SchedNeoverseN2.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedPredAmpere.td
[AArch64] Support for Ampere1 core
2022-05-03 15:54:02 +01:00
AArch64SchedPredExynos.td
[AArch64][SchedModels] Handle virtual registers in FP/NEON predicates
2022-02-17 13:41:05 +03:00
AArch64SchedPredicates.td
[AArch64] Support for Ampere1 core
2022-05-03 15:54:02 +01:00
AArch64SchedThunderX2T99.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedThunderX3T110.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedThunderX.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64SchedTSV110.td
[AArch64] Initial sched model for Neoverse N2
2022-07-08 09:39:13 +00:00
AArch64Schedule.td
…
AArch64SelectionDAGInfo.cpp
[clang] Add support for __builtin_memset_inline
2022-06-10 13:13:59 +00:00
AArch64SelectionDAGInfo.h
[clang] Add support for __builtin_memset_inline
2022-06-10 13:13:59 +00:00
AArch64SIMDInstrOpt.cpp
[llvm] Use nullptr instead of 0 (NFC)
2021-12-28 08:52:25 -08:00
AArch64SLSHardening.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
AArch64SMEInstrInfo.td
[AArch64][SME] Add SVE2 psel, uclamp, sclamp and revd IR intrinsics
2022-06-28 10:25:06 +01:00
AArch64SpeculationHardening.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
AArch64StackTagging.cpp
[MTE] [HWASan] Use LoopInfo for reachability queries.
2022-06-22 15:28:49 -07:00
AArch64StackTaggingPreRA.cpp
Remove unneeded cl::ZeroOrMore for cl::opt/cl::list options
2022-06-05 00:31:44 -07:00
AArch64StorePairSuppress.cpp
…
AArch64Subtarget.cpp
[AArch64] Add -aarch64-insert-extract-base-cost
2022-05-05 10:35:45 +00:00
AArch64Subtarget.h
[AArch64] Add -aarch64-insert-extract-base-cost
2022-05-05 10:35:45 +00:00
AArch64SVEInstrInfo.td
[AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD
2022-07-21 10:56:43 +00:00
AArch64SystemOperands.td
[AArch64] Add target feature "all"
2022-06-30 10:37:58 -07:00
AArch64TargetMachine.cpp
[llvm] Don't use Optional::getValue (NFC)
2022-06-20 22:45:45 -07:00
AArch64TargetMachine.h
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
AArch64TargetObjectFile.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
AArch64TargetObjectFile.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AArch64TargetTransformInfo.cpp
[AArch64] Add target hook for preferPredicateOverEpilogue
2022-07-21 17:20:06 +01:00
AArch64TargetTransformInfo.h
[AArch64] Add target hook for preferPredicateOverEpilogue
2022-07-21 17:20:06 +01:00
CMakeLists.txt
[AArch64] Order STP Q's by ascending address
2022-05-23 09:50:44 +01:00
SMEInstrFormats.td
[AArch64][SME] Add SME addha/va intrinsics
2022-07-05 09:47:17 +01:00
SVEInstrFormats.td
[AArch64][SVE] Ensure PTEST operands have type nxv16i1
2022-07-12 09:27:59 +01:00
SVEIntrinsicOpts.cpp
[IR] Move vector.insert/vector.extract out of experimental namespace
2022-06-27 10:48:45 +00:00