1a8468ba61
Initial optimization is to convert (i64 (zext (i32 X))) to (i64 (sext (i32 X))) if the dominating condition for the basic block guaranteed the sign bit of X is zero. This frequently occurs in loop preheaders where a signed induction variable that can never be negative has been widened. There will be a dominating check that the 32-bit trip count isn't negative or zero. The check here is not restricted to that specific case though. A i32->i64 sext is cheaper than zext on RV64 without the Zba extension. Later optimizations can often remove the sext from the preheader basic block because the dominating block also needs a sext to evaluate the greater than 0 check. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D129732
74 lines
2.5 KiB
C++
74 lines
2.5 KiB
C++
//===-- RISCV.h - Top-level interface for RISCV -----------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// RISC-V back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCV_H
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#define LLVM_LIB_TARGET_RISCV_RISCV_H
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class RISCVRegisterBankInfo;
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class RISCVSubtarget;
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class RISCVTargetMachine;
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class AsmPrinter;
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class FunctionPass;
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class InstructionSelector;
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class MCInst;
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class MCOperand;
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class MachineInstr;
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class MachineOperand;
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class PassRegistry;
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FunctionPass *createRISCVCodeGenPreparePass();
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void initializeRISCVCodeGenPreparePass(PassRegistry &);
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bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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AsmPrinter &AP);
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bool lowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp, const AsmPrinter &AP);
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FunctionPass *createRISCVISelDag(RISCVTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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FunctionPass *createRISCVMakeCompressibleOptPass();
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void initializeRISCVMakeCompressibleOptPass(PassRegistry &);
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FunctionPass *createRISCVGatherScatterLoweringPass();
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void initializeRISCVGatherScatterLoweringPass(PassRegistry &);
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FunctionPass *createRISCVSExtWRemovalPass();
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void initializeRISCVSExtWRemovalPass(PassRegistry &);
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FunctionPass *createRISCVMergeBaseOffsetOptPass();
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void initializeRISCVMergeBaseOffsetOptPass(PassRegistry &);
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FunctionPass *createRISCVExpandPseudoPass();
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void initializeRISCVExpandPseudoPass(PassRegistry &);
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FunctionPass *createRISCVExpandAtomicPseudoPass();
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void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
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FunctionPass *createRISCVInsertVSETVLIPass();
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void initializeRISCVInsertVSETVLIPass(PassRegistry &);
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FunctionPass *createRISCVRedundantCopyEliminationPass();
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void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
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InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
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RISCVSubtarget &,
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RISCVRegisterBankInfo &);
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}
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#endif
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