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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel
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Matt Arsenault 8d0383eb69 CodeGen: Remove AliasAnalysis from regalloc 
This was stored in LiveIntervals, but not actually used for anything
related to LiveIntervals. It was only used in one check for if a load
instruction is rematerializable. I also don't think this was entirely
correct, since it was implicitly assuming constant loads are also
dereferenceable.

Remove this and rely only on the invariant+dereferenceable flags in
the memory operand. Set the flag based on the AA query upfront. This
should have the same net benefit, but has the possible disadvantage of
making this AA query nonlazy.

Preserve the behavior of assuming pointsToConstantMemory implying
dereferenceable for now, but maybe this should be changed.
2022-07-18 17:23:41 -04:00
..
arm64-atomic-128.ll
AArch64: use indivisible cmpxchg for 128-bit atomic loads at O0
2021-09-22 14:20:43 +01:00
arm64-atomic.ll
[AArch64] Fix subtarget features for tests. NFC
2022-07-12 11:03:40 +01:00
arm64-callingconv-ios.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
arm64-callingconv.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
arm64-fallback.ll
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
2022-01-06 14:23:51 +01:00
arm64-irtranslator-fmuladd.ll
…
arm64-irtranslator-gep.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-irtranslator-stackprotect.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
arm64-irtranslator-switch.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
arm64-irtranslator.ll
[OpaquePtr][AArch64] Use elementtype on ldxr/stxr
2022-03-14 10:09:59 -07:00
arm64-regbankselect.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
artifact-combine-unmerge.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
artifact-find-value.mir
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
assert-align.ll
Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
2022-01-24 09:26:52 -05:00
builtin-return-address-pacret.ll
Reapply "RegAllocFast: Rewrite and improve"
2020-09-30 10:35:25 -04:00
byval-call.ll
[AArch64] Async unwind - function epilogues
2022-04-12 16:50:50 +01:00
call-lowering-const-bitcast-func.ll
…
call-lowering-i128-on-stack.ll
…
call-lowering-i256-crash.ll
…
call-lowering-signext.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
call-lowering-sret-demotion.ll
[AArch64][GlobalISel] Add support for sret demotion.
2022-07-05 15:23:47 -07:00
call-lowering-vectors.ll
[AArch64][GlobalISel] Fix call lowering for <3 x i32> vector arguments
2022-07-08 10:25:45 +02:00
call-lowering-zeroext.ll
[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress
2021-08-02 14:48:44 -07:00
call-translator-cse.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
call-translator-ios.ll
[AArch64][GlobalISel] Emit extloads for ZExt/SExt values in assignValueToAddress
2021-08-02 14:48:44 -07:00
call-translator-musttail.ll
…
call-translator-tail-call-sret.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
call-translator-tail-call-weak.ll
[NFC] Removed unused prefixes in llvm/test/CodeGen/AArch64
2020-12-09 12:47:51 -08:00
call-translator-tail-call.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
call-translator-variadic-musttail.ll
[AArch64] Order STP Q's by ascending address
2022-05-23 09:50:44 +01:00
call-translator.ll
[AArch64] Emit AssertZExt for i1 arguments
2021-10-11 11:55:11 +03:00
combine-add.mir
[GISel] Add new combines for G_ADD
2022-06-06 11:19:45 -07:00
combine-and-or-disjoint-mask.mir
Fix an or+and miscompile w/ GlobalISel
2022-05-18 19:09:47 -07:00
combine-anyext-crash.mir
…
combine-build-vector.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-copy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-ext-debugloc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-ext.mir
GlobalISel: Add combines for extend operations
2020-09-01 08:50:06 -07:00
combine-extract-vec-elt.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-fabs.mir
[GISel] Add new combines for unary FP instrs with constant operand
2020-09-16 10:34:15 -07:00
combine-fconstant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-flog2.mir
[GISel] Add new combines for unary FP instrs with constant operand
2020-09-16 10:34:15 -07:00
combine-fminimum-fmaximum.mir
[GISel] Add new combines for G_FMINNUM/MAXNUM and G_FMINIMUM/MAXIMUM
2022-05-18 12:08:53 -07:00
combine-fminnum-fmaxnum.mir
[GISel] Add new combines for G_FMINNUM/MAXNUM and G_FMINIMUM/MAXIMUM
2022-05-18 12:08:53 -07:00
combine-fneg.mir
[GISel] Add new combines for unary FP instrs with constant operand
2020-09-16 10:34:15 -07:00
combine-fptrunc.mir
[GISel] Add new combines for unary FP instrs with constant operand
2020-09-16 10:34:15 -07:00
combine-fsqrt.mir
[GISel] Add new combines for unary FP instrs with constant operand
2020-09-16 10:34:15 -07:00
combine-icmp-to-lhs-known-bits.mir
Add missing REQUIRES: asserts to combine-icmp-to-lhs-known-bits.mir
2021-09-03 09:25:37 -07:00
combine-insert-vec-elt.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
combine-inttoptr-ptrtoint.mir
[GISel] Add combiners for G_INTTOPTR and G_PTRTOINT
2020-07-31 10:13:36 -07:00
combine-mul-to-shl.mir
…
combine-mul.mir
[GlobalISel] Extend CombinerHelper::matchConstantOp() to match constant splat vectors.
2021-09-30 14:31:25 -07:00
combine-mulo-with-2.mir
[GlobalISel] Combine mulo x, 2 -> addo x, x
2021-09-28 16:59:43 -07:00
combine-ptradd-int2ptr.mir
[GlobalISel] Fix incorrect sign extension when combining G_INTTOPTR and G_PTR_ADD
2022-01-20 17:02:52 +00:00
combine-ptradd-reassociation.mir
[GlobalISel] Make G_PTR_ADD pattern matcher non-commutative.
2021-12-09 12:38:16 -08:00
combine-ptrtoint.mir
[GISel] Add combiners for G_INTTOPTR and G_PTRTOINT
2020-07-31 10:13:36 -07:00
combine-select.mir
[AArch64][GlobalISel] Implement combines for boolean G_SELECT->bitwise ops.
2022-02-20 00:53:09 -08:00
combine-sext-debugloc.mir
…
combine-sext-trunc-sextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-shift-immed-mismatch-crash.mir
[IR] Enable opaque pointers by default
2022-06-02 09:40:56 +02:00
combine-shift-of-shifted-dbg-value-fallback.ll
[AArch64] Split fuse-literals feature
2022-04-11 05:27:11 +00:00
combine-shl.mir
GlobalISel: Combine op undef, x to 0
2020-09-08 09:46:38 -07:00
combine-trunc.mir
GlobalISel: Fix truncating shift amount in trunc (shl) combine
2020-09-23 09:07:50 -04:00
combine-udiv.ll
[SchedModels][CortexA55] Add ASIMD integer instructions
2022-02-17 13:41:57 +03:00
combine-udiv.mir
[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.
2021-10-12 11:31:22 -07:00
combine-umulh-to-lshr.mir
[GlobalISel] Add support for constant vector folding of binops in CSEMIRBuilder.
2021-10-12 11:31:22 -07:00
combine-unmerge.mir
[GlobalISel] Add a X, Y = G_UNMERGE(G_ZEXT Z) -> X = G_ZEXT Z; Y = 0 combine
2020-09-14 17:27:23 -07:00
combiner-load-store-indexing.ll
…
constant-dbg-loc.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
constant-mir-debugify.mir
[DIBuilder] Do not replace empty enum types
2021-08-30 12:33:03 -07:00
contract-store.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
darwin-tls-call-clobber.ll
Reapply "RegAllocFast: Rewrite and improve"
2020-09-30 10:35:25 -04:00
debug-cpp.ll
…
debug-insts.ll
[GlobalISel][test] Add REQUIRES: asserts after D76934
2020-06-11 13:50:56 -07:00
debug-loc-legalize-tail-call.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
dynamic-alloca-lifetime.ll
…
dynamic-alloca.ll
…
fallback-nofastisel.ll
…
fconstant-dbg-loc.ll
…
fold-brcond-fcmp.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
fold-fp-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
fold-global-offsets-target-features.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
fold-global-offsets.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fold-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
form-bitfield-extract-from-and.mir
[GlobalISel][AArch64] Combine and (lshr x, cst), mask -> ubfx x, cst, width
2021-06-01 10:56:17 -07:00
form-bitfield-extract-from-sextinreg.mir
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
2021-04-29 21:54:19 -04:00
form-bitfield-extract-from-shr-and.mir
Fix zero-width bitfield extracts to emit 0
2022-05-03 14:46:42 -07:00
form-bitfield-extract-from-shr.mir
[GlobalISel] Combine shr(shl x, c1), c2 to G_SBFX/G_UBFX
2021-08-05 13:52:10 +02:00
fp16-copy-gpr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp128-legalize-crash-pr35690.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
freeze.ll
[AArch64InstPrinter] Change printAddSubImm to comment imm value when shifted
2021-08-03 02:28:46 -07:00
gisel-abort.ll
…
gisel-commandline-option-fastisel.ll
…
gisel-commandline-option.ll
CodeGen: Remove AliasAnalysis from regalloc
2022-07-18 17:23:41 -04:00
gisel-fail-intermediate-legalizer.ll
…
huge-switch.ll
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
implicit_def_rbs_crash.mir
[GlobalISel] Fix crash in RBS with a non-generic IMPLICIT_DEF.
2021-03-24 23:08:51 -07:00
inline-asm.ll
…
inline-memcpy-forced.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-memcpy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-memmove.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-memset.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
inline-small-memcpy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
integration-shuffle-vector.ll
…
inttoptr_add.ll
[GlobalISel] Fix incorrect sign extension when combining G_INTTOPTR and G_PTR_ADD
2022-01-20 17:02:52 +00:00
irtranslator-arguments.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
irtranslator-atomic-metadata.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-bitcast.ll
…
irtranslator-block-order.ll
…
irtranslator-condbr-lower-tree.ll
[SimplifyCFG] Tail-merging all blocks with ret terminator
2021-06-24 13:15:39 +03:00
irtranslator-convert-fp16-intrinsics.ll
GlobalISel: Translate llvm.convert.{to|from}.fp16 intrinsics
2020-07-28 11:46:05 -04:00
irtranslator-delayed-stack-protector.ll
Revert "[GISel] Unify use of getStackGuard"
2022-07-12 17:00:43 -04:00
irtranslator-dilocation.ll
…
irtranslator-duplicate-types-param.ll
…
irtranslator-exceptions.ll
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
irtranslator-extends.ll
…
irtranslator-extract-used-by-dbg.ll
[[GlobalISel][IRTranslator] Fix a crash when the use of an extractvalue is a non-dominated metadata use.
2020-12-12 14:58:54 -08:00
irtranslator-fixed-point-intrinsics.ll
GlobalISel: Define mulfix/divfix opcodes
2020-07-24 20:02:20 -04:00
irtranslator-fp-min-max-intrinsics.ll
…
irtranslator-indirect-br-repeated-block.ll
…
irtranslator-inline-asm.ll
[Tests] Add elementtype attribute to indirect inline asm operands (NFC)
2022-01-06 14:23:51 +01:00
irtranslator-invoke-probabilities.ll
[CodeGen] Add "noreturn" attirbute to _Unwind_Resume
2020-12-24 18:14:18 +07:00
irtranslator-load-metadata.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-localescape.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-max-address-space.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-memcpy-inline.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-memfunc-undef.ll
…
irtranslator-no-op-intrinsics.ll
Try to fix buildbots after d3205bbca3e0002d76282878986993e7e7994779
2020-10-26 11:49:21 +01:00
irtranslator-no-unwind-inline-asm.ll
Support unwinding from inline assembly
2021-05-13 19:13:03 +01:00
irtranslator-one-by-n-vector-ptr-add.ll
[GlobalISel] Translate <1 x N> getelementptrs to scalar G_PTR_ADDs
2021-07-01 16:38:47 -07:00
irtranslator-reductions.ll
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
2021-05-05 17:35:02 -04:00
irtranslator-split-vector-arg.ll
…
irtranslator-stack-evt-bug47619.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-stack-objects.ll
[CallLowering] Support opaque pointers
2021-09-10 18:32:12 +02:00
irtranslator-stack-protector-windows.ll
[GlobalIsel] Fix fallback if stack protector isn't supported.
2022-05-13 14:17:27 -07:00
irtranslator-store-metadata.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-switch-bittest.ll
[GlobalISel][IRTranslator] Fix crash during bit-test switch optimization with odd types.
2021-09-24 00:19:27 -07:00
irtranslator-tbaa.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
irtranslator-unreachable.ll
Revert "Revert "[GlobalISel][IRTranslator] Emit trap intrinsic for "unreachable"""
2021-10-06 04:16:19 -07:00
irtranslator-unwind-inline-asm.ll
[GlobalISel] Ensure that translateInvoke adds all successors for inlineasm
2021-11-09 16:20:34 -08:00
irtranslator-volatile-load-pr36018.ll
…
irtranslator-weird-alloca-size.ll
…
labels-are-not-dead.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-abs.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-add.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-and.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-atomicrmw.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-bitreverse.mir
[AArch64][GlobalISel] Legalize non-register-sized scalar G_BITREVERSE
2021-08-20 14:44:03 -07:00
legalize-blockaddress.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-bswap.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-build-vector.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-bzero-unsupported.mir
[AArch64][GlobalISel] Emit bzero on Darwin
2021-03-25 17:14:25 -07:00
legalize-bzero.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-ceil.mir
…
legalize-cmp.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-cmpxchg-128.mir
AArch64: do not use xzr for ldxp -> stxp dataflow.
2022-02-09 12:29:16 +00:00
legalize-cmpxchg-with-success.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-cmpxchg.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-combines.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-concat-vectors.mir
[AArch64][GlobalISel] Mark v16s8 <- v8s8, v8s8 G_CONCAT_VECTOR as legal
2021-08-05 09:40:46 -07:00
legalize-constant.mir
[GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT.
2022-07-14 11:05:10 -07:00
legalize-cos.mir
…
legalize-ctlz.mir
[AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
2021-03-23 12:49:10 -07:00
legalize-ctpop-no-implicit-float.mir
[AArch64][GlobalISel] Implement custom legalization for s32 and s64 G_CTPOP
2021-04-19 10:56:02 -07:00
legalize-ctpop.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-cttz-zero-undef.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-cttz.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-div.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-divrem.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-dyn-alloca.mir
…
legalize-exceptions.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-exp.mir
…
legalize-ext-cse.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-ext-csedebug-output.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-ext.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-extload.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-extract-vector-elt.mir
[GlobalISel] Widen G_EXTRACT_VECTOR_ELT using anyext instead of sext.
2021-10-04 12:19:19 -07:00
legalize-extracts.mir
[GlobalISel] NFC: Add test coverage for s144 and s142
2022-04-05 15:26:46 -07:00
legalize-fcmp.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-fexp2.mir
…
legalize-fma.mir
…
legalize-fmaximum.mir
[AArch64][GlobalISel] Legalize scalar G_FMAXIMUM + G_FMINIMUM
2021-12-09 11:54:14 -08:00
legalize-fmaxnum.mir
[AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM
2021-08-18 13:30:03 -07:00
legalize-fminimum.mir
[AArch64][GlobalISel] Legalize scalar G_FMAXIMUM + G_FMINIMUM
2021-12-09 11:54:14 -08:00
legalize-fminnum.mir
[AArch64][GlobalISel] Legalize scalar G_FMINNUM + G_FMAXNUM
2021-08-18 13:30:03 -07:00
legalize-fp16-fconstant.mir
[GlobalISel] Change widenScalar of G_FCONSTANT to mutate into G_CONSTANT.
2022-07-14 11:05:10 -07:00
legalize-fp128-fconstant.mir
[AArch64][GlobalISel] Add support for FCONSTANT of FP128 type
2021-01-13 10:46:10 -05:00
legalize-fp-arith-fp16.mir
[AArch64][GlobalISel] Legalize narrow scalar FP arithmetic
2021-08-24 13:54:28 -07:00
legalize-fp-arith.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-fpext.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-fptoi.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-fptrunc.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
legalize-freeze.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-frint.mir
…
legalize-fshl.mir
[AArch64][GlobalISel] Lower G_FSHL and G_FSHR.
2021-03-23 16:09:19 -07:00
legalize-fshr.mir
[AArch64][GlobalISel] Add test for G_FSHR legalization.
2021-03-23 16:11:45 -07:00
legalize-global-pic.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
legalize-global.mir
Recommit "[AArch64][GlobalISel] Fold constants into G_GLOBAL_VALUE"
2021-03-18 16:01:02 -07:00
legalize-ignore-hint.mir
[GlobalISel] Add G_ASSERT_ZEXT
2021-01-28 13:58:37 -08:00
legalize-ignore-non-generic.mir
…
legalize-insert-vector-elt.mir
[AArch64][GlobalISel] Make <8 x s16> for G_INSERT_VECTOR_ELT legal.
2020-09-25 01:59:16 -07:00
legalize-inserts.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-intrinsic-get-dynamic-area-offset.mir
[AArch64][GlobalISel] Add legalizer support for the @llvm.get.dynamic.area.offset intrinsic.
2021-08-20 17:13:34 -07:00
legalize-intrinsic-min-max.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-intrinsic-round.mir
…
legalize-intrinsic-trunc.mir
…
legalize-inttoptr-xfail-1.mir
…
legalize-inttoptr-xfail-2.mir
…
legalize-inttoptr.mir
[AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal
2021-07-13 17:28:14 -07:00
legalize-itofp.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-llround.mir
[AArch64][GlobalISel] Legalize G_LLROUND for s64 + s32
2021-08-23 09:45:23 -07:00
legalize-load-store-fewerElts.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-load-store-vector-of-ptr-debugloc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-load-store-vector-of-ptr.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-load-store.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-load-trunc.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-log2.mir
…
legalize-log10.mir
…
legalize-log.mir
…
legalize-lrint.mir
[AArch64][GlobalISel] Add legalization & selection support for G_INTRINSIC_LRINT.
2020-07-30 16:14:56 -07:00
legalize-lround.mir
[AArch64][GlobalISel] Mark G_LROUND as legal for s64 dst + s32/s64 src.
2021-08-20 14:22:58 -07:00
legalize-memcpy-et-al.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-memcpy-with-debug-info.mir
[llvm] Inclusive language: replace master with main in file paths in LIT tests
2021-11-08 12:39:50 -06:00
legalize-memlib-debug-loc.mir
[GlobalISel] Mark memcpy/memmove/memset as thisreturn
2021-07-20 17:04:33 -07:00
legalize-merge-values.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-min-max.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-mul.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-nearbyint.mir
…
legalize-non-pow2-load-store.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-or.mir
[GlobalISel] NFC: Regen some tests + improve test coverage for wide even types
2022-04-05 12:13:22 -07:00
legalize-phi-insertpt-decrement.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-phi.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-pow.mir
…
legalize-property.mir
…
legalize-ptr-add.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-ptrtoint.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-add.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-and.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-fadd.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-or.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-reduce-xor.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-rem.mir
AArch64/GlobalISel: Remove pointless s1 legalize rules
2022-04-12 16:54:04 -04:00
legalize-rotr-rotl.mir
[AArch64][GlobalISel] Define some legalization rules for G_ROTR and G_ROTL.
2021-03-30 11:11:19 -07:00
legalize-s128-div.mir
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
legalize-sadde.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-saddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-saddsat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sbfx.mir
[GlobalISel] Allow different types for G_SBFX and G_UBFX operands
2021-04-02 11:11:06 -04:00
legalize-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sext-128.ll
…
legalize-sext-128.mir
…
legalize-sext-copy.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-sext-zext-128.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-sext.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-sextload.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-shift-imm-promote-dloc.mir
[AArch64][GlobalISel] Add more specific debug info tests for 613f12dd8e2403f5630ab299d2a1bb2cb111ead1.
2020-07-09 17:13:16 -07:00
legalize-shift.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-shuffle-vector.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-simple.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sin.mir
…
legalize-sqrt.mir
…
legalize-ssube.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-ssubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-ssubsat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-sub.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-uadd-sat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-uadde.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-uaddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-ubfx.mir
[GlobalISel] Allow different types for G_SBFX and G_UBFX operands
2021-04-02 11:11:06 -04:00
legalize-undef.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-unmerge-values.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-usub-sat.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-usube.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-usubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalize-vaarg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-vacopy.mir
AArch64: support @llvm.va_copy in GISel
2021-08-10 13:11:03 +01:00
legalize-vector-cmp.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-vector-shift.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-xor.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalize-zextload.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
legalizer-combiner-zext-trunc-crash.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
legalizer-combiner.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalizer-info-validation.mir
Replace hard coded number with regex so the test passes on downstream projects that may define additional opcodes.
2022-07-08 15:49:37 -07:00
lifetime-marker-no-dce.mir
[GlobalISel] Don't DCE LIFETIME_START/LIFETIME_END markers.
2021-03-17 18:02:08 -07:00
load-addressing-modes.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
load-wro-addressing-modes.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
localizer-arm64-tti.ll
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
localizer-in-O0-pipeline.mir
…
localizer.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
lower-neon-vector-fcmp.mir
[AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps
2021-05-10 15:40:06 -07:00
machine-cse-mid-pipeline.mir
…
memcpy_chk_no_tail.ll
…
merge-stores-truncating.ll
[AArch64][GlobalISel] combine and + [la]sr => ubfx
2021-10-18 10:33:01 -07:00
merge-stores-truncating.mir
[GlobalISel] Fix the stores of truncates -> wide store combine for non-evenly dividing type sizes.
2021-10-09 21:18:20 -07:00
no-neon-no-fp.ll
[AArch64][GlobalISel] Fall back if disabling neon/fp in the translator.
2021-03-17 15:08:08 -07:00
no-regclass.mir
…
non-pow-2-extload-combine.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
observer-change-crash.mir
…
opt-and-tbnz-tbz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-and-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-compare.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-ext-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-shift-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-trunc-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-fold-xor-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
opt-overlapping-and-postlegalize.mir
[AArch64][GlobalISel] Run overlapping_and after legalization
2021-09-28 17:13:34 -07:00
opt-overlapping-and.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
opt-shifted-reg-compare.mir
[AArch64][GlobalISel] Don't use explicit zero registers for compare results.
2020-10-14 16:49:33 -07:00
phi-mir-debugify.mir
[DIBuilder] Do not replace empty enum types
2021-08-30 12:33:03 -07:00
postlegalizer-combine-ptr-add-chain.mir
[AArch64][GlobalISel] Add ptradd_immed_chain combine to post-legalizer combiner.
2021-08-11 13:59:23 -07:00
postlegalizer-combiner-and-trivial-mask.mir
[GlobalISel] Implement computeKnownBits for G_ASSERT_ZEXT
2021-01-28 16:34:34 -08:00
postlegalizer-combiner-anyext-to-zext.mir
[AArch64][GlobalISel] Change G_ANYEXT fed by scalar G_ICMP to G_ZEXT
2021-10-01 15:01:20 -07:00
postlegalizer-combiner-constant-fold.mir
[GlobalISel] Add a constant folding combine.
2021-07-26 14:53:33 -07:00
postlegalizer-combiner-copy-prop.mir
[GlobalISel] Enable copy-propagation in post-legalizer combiner.
2020-08-15 13:44:30 -07:00
postlegalizer-combiner-identity.mir
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
2021-07-26 15:17:11 -07:00
postlegalizer-combiner-merge.mir
[AArch4][GlobalISel] Post-legalize combine s64 = G_MERGE s32, 0 -> G_ZEXT.
2021-07-26 10:58:04 -07:00
postlegalizer-combiner-redundant-sextinreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizer-combiner-split-zero-stores.mir
AArch64/GlobalISel: Fix memory type in test
2021-12-20 19:11:48 -05:00
postlegalizer-combiner-undef.mir
[AArch64][GlobalISel] Add undef combines to postlegalizer combiner.
2022-05-05 09:22:08 -07:00
postlegalizer-lowering-adjust-icmp-imm.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
postlegalizer-lowering-build-vector-to-dup.mir
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
postlegalizer-lowering-ext.mir
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
2020-10-22 14:43:25 -07:00
postlegalizer-lowering-rev.mir
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
2020-10-22 14:43:25 -07:00
postlegalizer-lowering-shuf-to-ins.mir
Recommit "[AArch64][GlobalISel] Match G_SHUFFLE_VECTOR -> insert elt + extract elt"
2021-02-23 11:55:16 -08:00
postlegalizer-lowering-shuffle-duplane.mir
[AArch64][GlobalISel] Form G_DUPLANE32 for <2 x s32> shufflevectors in lowering.
2021-03-09 11:36:26 -08:00
postlegalizer-lowering-shuffle-splat.mir
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
2020-10-22 14:43:25 -07:00
postlegalizer-lowering-swap-compare-operands.mir
[AArch64][GlobalISel] Swap compare operands when it may be profitable
2021-04-09 15:46:48 -07:00
postlegalizer-lowering-trn.mir
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
2020-10-22 14:43:25 -07:00
postlegalizer-lowering-truncstore.mir
[AArch64][GlobalISel] Don't form truncstores in postlegalizer-lowering for s128.
2021-07-20 00:04:34 -07:00
postlegalizer-lowering-uzp.mir
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
2020-10-22 14:43:25 -07:00
postlegalizer-lowering-vashr-vlshr.mir
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
postlegalizer-lowering-zip.mir
[AArch64][GlobalISel] Split post-legalizer combiner to allow for lowering at -O0
2020-10-22 14:43:25 -07:00
postlegalizercombiner-extending-loads.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizercombiner-extractvec-faddp.mir
[AArch64][GlobalISel] Add combine for G_EXTRACT_VECTOR_ELT to allow selection of pairwise FADD.
2020-11-03 17:25:14 -08:00
postlegalizercombiner-hoist-same-hands.mir
[GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
2020-08-11 10:40:06 -07:00
postlegalizercombiner-mulpow2.mir
[AArch64][GlobalISel] Don't perform the mul const combine with G_PTR_ADD
2021-02-10 15:30:45 -08:00
postlegalizercombiner-rotate.mir
[GlobalISel] Add G_ROTL and G_ROTR to right_identity_zero
2021-09-08 10:09:02 -07:00
postlegalizercombiner-select.mir
[AArch64][GlobalISel] Add identity combines to post-legal combiner.
2021-07-26 15:17:11 -07:00
postselectopt-constrain-new-regop.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postselectopt-dead-cc-defs-in-fcmp.mir
[AArch64][GlobalISel] Introduce a new post-isel optimization pass.
2020-10-23 10:18:36 -07:00
prelegalizer-combiner-addo-zero.mir
[GlobalISel] Combine (G_*ADDO x, 0) -> x + no carry out
2022-02-03 14:25:15 -08:00
prelegalizer-combiner-divrem-insertpt-crash.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizer-combiner-icmp-to-true-false-known-bits.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizer-combiner-load-and-mask.mir
[GlobalISel] Fix and(load)->zextload combine crash.
2022-07-13 14:58:45 -07:00
prelegalizer-combiner-load-or-pattern-align.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizer-combiner-load-or-pattern.mir
[GlobalISel] Fix load-or combine moving loads across potential aliasing stores.
2021-07-19 10:23:23 -07:00
prelegalizer-combiner-mulo-zero.mir
[GlobalISel] Combine: (G_*MULO x, 0) -> 0 + no carry out
2022-02-03 14:23:58 -08:00
prelegalizer-combiner-narrow-binop-feeding-add.mir
[GlobalISel] Narrow binops feeding into G_AND with a mask
2021-08-13 18:31:13 -07:00
prelegalizercombiner-ashr-shl-to-sext-inreg.mir
[GlobalISel] Add a combine for ashr(shl x, c), c --> sext_inreg x, c'
2020-08-18 10:42:15 -07:00
prelegalizercombiner-binop-same-val.mir
…
prelegalizercombiner-br.mir
[GlobalISel] Check if branches use the same MBB in matchOptBrCondByInvertingCond
2021-02-02 15:38:48 -08:00
prelegalizercombiner-bzero.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-concat-vectors.mir
[GISel]: Few InsertVecElt combines
2020-10-28 12:27:07 -07:00
prelegalizercombiner-copy-prop-disabled.mir
[gicombiner] Allow disable-rule option to disable all-except-...
2020-06-16 16:57:16 -07:00
prelegalizercombiner-extending-loads-cornercases.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-extending-loads-s1.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-extending-loads.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-funnel-shifts-to-rotates.mir
[AArch64][GlobalISel] Combine funnel shifts to rotates.
2021-03-30 11:00:36 -07:00
prelegalizercombiner-hoist-same-hands.mir
[GlobalISel] Combine (logic_op (op x...), (op y...)) -> (op (logic_op x, y))
2020-08-11 10:40:06 -07:00
prelegalizercombiner-icmp-redundant-trunc.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-invert-cmp.mir
[GlobalISel] Extend not_cmp_fold to work on conditional expressions
2020-09-07 09:31:08 +01:00
prelegalizercombiner-not-really-equiv-insts.mir
[GlobalISel] Don't combine instructions which are fed by memory instructions using different size
2022-02-04 15:00:47 -08:00
prelegalizercombiner-prop-extends-phi.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-ptradd-chain.mir
[AArch64][GlobalISel] Relax oneuse restriction for PTR_ADD chain combining to check addressing legality.
2021-08-10 16:41:18 -07:00
prelegalizercombiner-select.mir
Recommit "[GlobalISel] Walk through hints in getDefIgnoringCopies et al"
2021-01-28 14:43:00 -08:00
prelegalizercombiner-sextload-from-sextinreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prelegalizercombiner-shuffle-vector.mir
…
prelegalizercombiner-simplify-add.mir
[GlobalISel] Simplify G_ADD when it has (0-X) on the LHS or RHS
2020-06-15 09:43:24 -07:00
prelegalizercombiner-trivial-arith.mir
[AArch64][GlobalISel] Fix combiner assertion in matchConstantOp().
2021-10-11 15:55:13 -07:00
prelegalizercombiner-undef.mir
[GlobalISel] Combine G_SHL, G_ASHR, G_SHL of undef shifts to undef.
2022-05-13 12:20:34 -07:00
prelegalizercombiner-xor-of-and-with-same-reg.mir
[GlobalISel] Combine (xor (and x, y), y) -> (and (not x), y)
2020-09-28 10:08:14 -07:00
preselect-process-phis.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
rbs-matrixindex-regclass-crash.mir
[AArch64][GlobalISel] Fix an crash in RBS due to a new regclass being added.
2021-10-29 11:47:00 -07:00
reg-bank-128bit.mir
…
regbank-assert-align.mir
Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
2022-01-24 09:26:52 -05:00
regbank-assert-sext.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-assert-zext.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-ceil.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbank-dup.mir
[AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr.
2021-02-21 21:17:29 -08:00
regbank-extract-vector-elt.mir
[AArch64][GlobalISel] Widen G_EXTRACT_VECTOR_ELT element types if < 8b.
2020-09-17 11:50:33 -07:00
regbank-extract.mir
[AArch64] Fix subtarget features for tests. NFC
2022-07-12 11:03:40 +01:00
regbank-fcmp.mir
[AArch64][GlobalISel] Fix regbankselect for G_FCMP with vector destinations
2021-04-21 18:11:30 -07:00
regbank-fma.mir
…
regbank-fmaximum.mir
[AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
2021-12-09 12:52:32 -08:00
regbank-fminimum.mir
[AArch64][GlobalISel] Add regbankselect support for G_FMAXIMUM/G_FMINIMUM
2021-12-09 12:52:32 -08:00
regbank-fp-use-def.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-inlineasm.mir
[AArch64][SME] Add load and store instructions
2021-07-16 10:11:10 +00:00
regbank-insert-vector-elt.mir
…
regbank-intrinsic-round.mir
…
regbank-intrinsic-trunc.mir
…
regbank-intrinsic.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbank-llround.mir
[AArch64][GlobalISel] Add regbankselect support for G_LLROUND
2021-08-23 10:32:20 -07:00
regbank-lround.mir
[AArch64][GlobalISel] Add regbankselect support for G_LROUND
2021-08-20 14:31:14 -07:00
regbank-maxnum.mir
[AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes
2021-08-18 13:32:19 -07:00
regbank-minnum.mir
[AArch64][GlobalISel] Mark G_FMINNUM/G_FMAXNUM as floating point opcodes
2021-08-18 13:32:19 -07:00
regbank-nearbyint.mir
…
regbank-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbank-shift-imm-64.mir
…
regbank-trunc-s128.mir
…
regbankselect-build-vector.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-dbg-value.mir
…
regbankselect-default.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
regbankselect-reductions.mir
[AArch64][GlobalISel] Regbankselect reductions to use FPR bank for scalars.
2020-10-16 10:42:15 -07:00
regbankselect-reg_sequence.mir
…
regbankselect-unmerge-vec.mir
…
ret-1x-vec.ll
GlobalISel: Merge and cleanup more AMDGPU call lowering code
2021-03-02 17:31:13 -05:00
ret-vec-promote.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
retry-artifact-combine.mir
[AArch64][test] Replace -march with -mtriple for llc RUN lines
2022-05-31 22:39:43 -07:00
select-abs.mir
[AArch64][GlobalISel] Mark some vector G_ABS cases as legal
2021-04-21 18:10:40 -07:00
select-add-low.mir
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
select-arith-extended-reg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-arith-shifted-reg.mir
…
select-atomic-load-store.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-atomicrmw.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-binop.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-bitcast-bigendian.mir
…
select-bitcast.mir
GlobalISel: Verify G_BITCAST changes the type
2020-07-08 17:16:27 -04:00
select-bitfield-insert.ll
[AArch64][GISel] and+or+shl => bfi
2021-06-17 12:52:59 -07:00
select-bitreverse.mir
[AArch64][GlobalISel] Mark some G_BITREVERSE types as legal + select them
2021-06-10 10:33:52 -07:00
select-blockaddress.mir
[GlobalISel] Clear unreachable blocks' contents after selection.
2021-10-05 23:06:22 -07:00
select-br.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-brcond-of-binop.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-bswap.mir
…
select-build-vector.mir
[AArch64][GlobalISel] Optimize G_BUILD_VECTOR of undef + 1 elt -> SUBREG_TO_REG
2021-08-26 11:45:11 -07:00
select-cbz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-ceil.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-cmp.mir
[AArch64][GlobalISel] Fold 64-bit cmps with 64-bit adds
2021-10-21 13:51:44 -07:00
select-cmpxchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-concat-vectors.mir
[AArch64][GlobalISel] Mark v16s8 <- v8s8, v8s8 G_CONCAT_VECTOR as legal
2021-08-05 09:40:46 -07:00
select-const-pool.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-const-vector.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-constant.mir
[GlobalISel] Rewrite the elide-br-by-swapping-icmp-ops combine to do less.
2020-09-09 13:08:16 -07:00
select-ctlz.mir
[AArch64][GlobalISel] Lower G_CTLZ_ZERO_UNDEF.
2021-03-23 12:49:10 -07:00
select-ctpop.mir
[AArch64][GlobalISel] Mark G_CTPOP as legal for v16s8 and v8s8
2021-04-13 11:03:39 -07:00
select-dbg-value.mir
[AArch64][GlobalISel] update the gisel test case
2022-07-07 11:43:42 +08:00
select-dup.mir
[AArch64][GlobalISel] Lower G_BUILD_VECTOR -> G_DUP
2021-03-08 13:01:10 -08:00
select-ext.mir
[AArch64][GlobaISel] Mark target generic instructions as HasNoSideEffects.
2021-05-11 12:38:53 -07:00
select-extload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-extract-vector-elt-with-extend.mir
[AArch64][GlobalISel] Fix crash in the extend(extract_vector_elt) optimization.
2021-09-23 23:07:16 -07:00
select-extract-vector-elt.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
select-extract.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
select-fabs.mir
…
select-faddp.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fcmp.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-floor.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fma.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fmul-indexed.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-fp16-fconstant.mir
[AArch64][GlobalISel] Select full-fp16 s16 G_FCONSTANT as a constant pool load
2021-09-10 19:36:34 -07:00
select-fp-casts.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-frameaddr.ll
…
select-frint-nofp16.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-frint.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-gv-cmodel-large.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-gv-cmodel-tiny.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-gv-with-offset.mir
[Aarch64] Correct register class for pseudo instructions
2021-09-09 14:31:49 -04:00
select-hint.mir
[AArch64][GlobalISel] update the test case with update_mir_test_checks.py
2022-07-07 09:03:32 +08:00
select-imm.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-implicit-def.mir
…
select-insert-extract.mir
…
select-insert-vector-elt.mir
Revert "Revert "[AArch64][GlobalISel] Add selection support for <8 x s16> G_INSERT_VECTOR_ELT with GPR scalar.""
2020-09-28 13:44:51 -07:00
select-int-ext.mir
[AArch64][GlobalISel] Prefer mov for s32->s64 G_ZEXT
2021-05-18 10:00:00 -07:00
select-int-ptr-casts.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-intrinsic-aarch64-hint.mir
…
select-intrinsic-aarch64-sdiv.mir
…
select-intrinsic-crypto-aesmc.mir
[AArch64] Fix subtarget features for tests. NFC
2022-07-12 11:03:40 +01:00
select-intrinsic-round.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-intrinsic-trunc.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-intrinsic-uaddlv.mir
[AArch64][GlobalISel] Regbankselect + select @llvm.aarch64.neon.uaddlv
2021-04-19 10:47:49 -07:00
select-jump-table-brjt-constrain.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-jump-table-brjt.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-ld2.mir
[AArch64][GlobalISel] Select @llvm.aarch64.neon.ld2.*
2021-08-23 17:15:53 -07:00
select-ld4.mir
[AArch64][GlobalISel] Select @llvm.aarch64.neon.ld4.*
2021-08-24 09:03:49 -07:00
select-ldaxr-intrin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-ldxr-intrin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-load-store-vector-of-ptr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-load.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-logical-imm.mir
…
select-logical-shifted-reg.mir
…
select-mul.mir
[AArch64][GlobalISel] Add selection tests for vector G_UMULH/G_SMULH.
2021-09-29 02:55:08 -07:00
select-muladd.mir
…
select-nearbyint.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-neon-vcvtfxu2fp.mir
…
select-neon-vector-fcmp.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-phi.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-pr32733.mir
…
select-property.mir
…
select-ptr-add.mir
[AArch64][GlobalISel] Optimize G_PTR_ADD with a negated offset to be a G_SUB.
2020-11-11 22:46:53 -08:00
select-reduce-add.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-reduce-fadd.mir
[AArch64][GlobalISel] Add selection support for v2s32 and v2s64 reductions for FADD/ADD.
2020-10-16 11:41:57 -07:00
select-redundant-zext-of-load.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-redundant-zext.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-returnaddr.ll
[AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET
2020-09-24 18:04:37 +01:00
select-returnaddress-liveins.mir
[AArch64][GlobalISel] Implement __builtin_return_address for PAC-RET
2020-09-24 18:04:37 +01:00
select-rev.mir
[AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes
2020-06-12 09:39:46 -07:00
select-rotate.mir
[AArch64][GlobalISel] Support for folding G_ROTR as shifted operands.
2021-09-02 21:37:24 -07:00
select-saddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-sbfx.mir
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
2021-04-29 21:54:19 -04:00
select-scalar-merge.mir
…
select-scalar-shift-imm.mir
AArch64 GIsel: legalize lshr operands, even if it is poison
2021-11-30 15:28:35 -05:00
select-select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-sextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-shuffle-vector.mir
[AArch64][GlobalISel] Selection support for vector DUP[X]lane instructions.
2020-07-29 11:41:37 -07:00
select-shufflevec-undef-mask-elt.mir
…
select-sqrt.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-ssubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-st2.mir
[AArch64][GlobalISel] Select llvm.aarch64.neon.st2 intrinsics
2021-07-20 13:23:46 -07:00
select-static.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-stlxr-intrin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-store-truncating-float.mir
[AArch64][GlobalISel] Fix incorrect handling of fp truncating stores.
2021-08-24 16:07:00 -07:00
select-store.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-stx.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
select-trap.mir
…
select-trn.mir
[AArch64][GlobalISel] Set hasSideEffects = 0 on custom shuffle opcodes
2020-06-12 09:39:46 -07:00
select-trunc.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-truncstore-atomic.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-uaddo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-ubfx.mir
[AArch64][GlobalISel] Fix width value for G_SBFX/G_UBFX
2021-04-29 21:54:19 -04:00
select-unmerge.mir
[AArch64] Rename CPY to DUP. NFC
2022-01-05 20:02:39 +00:00
select-unreachable-blocks.mir
[GlobalISel] Clear unreachable blocks' contents after selection.
2021-10-05 23:06:22 -07:00
select-usubo.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
select-uzp.mir
[AArch64][GlobalISel] Select uzp1 and uzp2
2020-06-03 15:09:41 -07:00
select-vector-icmp.mir
[AArch64][GlobalISel] Improve codegen for some constant vectors by using constant pool loads.
2020-06-23 19:23:47 -07:00
select-vector-shift.mir
[AArch64][GlobalISel] Fix incorrect codegen for <16 x s8> G_ASHR.
2021-04-09 10:41:41 -07:00
select-with-no-legality-check.mir
[AArch64] Add mayRaiseFPException to appropriate instructions
2022-04-14 16:51:22 +01:00
select-xor.mir
[AArch64][GlobalISel] Don't emit a branch for a fallthrough G_BR at -O0.
2020-09-10 15:01:26 -07:00
select-zext-as-copy.mir
AArch64/GlobalISel: Regenerate mir test checks
2022-04-11 20:12:22 -04:00
select-zextload.mir
GlobalISel: Allow forming atomic/volatile G_ZEXTLOAD
2022-07-08 11:55:08 -04:00
select-zip.mir
[AArch64][GlobalISel] Select zip1 and zip2
2020-06-02 18:57:11 -07:00
select.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
sext-inreg-ldrow-16b.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
speculative-hardening-brcond.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
store-addressing-modes.mir
AArch64/GlobalISel: Update tests to use correct memory types
2021-07-16 11:41:32 -04:00
store-merging.ll
[GlobalISel] Fix store merging incorrectly merging volatile stores.
2022-03-14 13:48:51 -07:00
store-merging.mir
[GlobalISel] Add a store-merging optimization pass and enable for AArch64.
2021-11-15 21:10:39 -08:00
store-wro-addressing-modes.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
subreg-copy.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
swifterror.ll
[AArch64] Make -mcpu=generic schedule for an in-order core
2021-10-09 15:58:31 +01:00
swiftself.ll
[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
2022-02-18 16:10:56 +00:00
tail-call-no-save-fp-lr.ll
…
tbnz-slt.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
tbz-sgt.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
translate-constant-dag.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
translate-gep.ll
…
translate-ret.ll
AArch64: support i128 (& larger) returns in GlobalISel
2021-07-26 14:16:35 +01:00
uaddo-8-16-bits.mir
[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.
2021-12-05 15:55:59 -05:00
ubsantrap.ll
AArch64: use correct operand for ubsantrap immediate.
2020-12-09 10:17:16 +00:00
unknown-intrinsic.ll
…
unwind-inline-asm.ll
Support unwinding from inline assembly
2021-05-13 19:13:03 +01:00
v8.4-atomic-128.ll
AArch64: use ldp/stp for 128-bit atomic load/store in v.84 onwards
2021-09-20 09:50:11 +01:00
varargs-ios-translator.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vastart.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vec-s16-param.ll
[AArch64][GlobalISel] Support lowering <1 x i8> arguments.
2021-02-22 13:58:44 -08:00
widen-narrow-tbz-tbnz.mir
AArch64/GlobalISel: Stop using legal s1 values
2022-07-08 11:55:08 -04:00
xro-addressing-mode-constant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00