pkarveti
4444f517e9
[Hexagon] Optimize load/store instruction during widening ( #186962 )
...
This change enhances the Hexagon Load-Store Widening pass to recognize
and optimize a specific pattern involving the S2_addasl_rrri
instruction. When widening loads/stores, the pass now detects cases
where the base register is defined by an S2_addasl_rrri instruction and
combines the operations into a single load double/store double
instruction with register shift op, eliminating the intermediate address
calculation.
Eg, for load,
If the definition of the base register came from a addasl instruction,
we generate a
memd(Rs + Rt << #imm) instead of memd(Rs + #imm) instruction.
Transform:
%18 = S2_addasl_rrri %8, %17, 3
%19 = L2_loadri_io %18, 0
to
%19 = L4_loadrd_rr %8, %17, 3
Patch By: Pavani Karveti <pkarveti@qti.qulacomm.com>
Author: Santanu Das <santdas@qti.qualcomm.com>
Co-authored-by: quic-santdas <quic_santdas@quicinc.com>
2026-03-24 11:41:24 +05:30
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