219 lines
9.3 KiB
TableGen
219 lines
9.3 KiB
TableGen
//===-- PPCOperands.td - PowerPC instruction operands -------*- tablegen -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines PowerPC instruction operands, including immediate
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// operands and addressing modes.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Immediate operand base classes
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//===----------------------------------------------------------------------===//
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// Base class for immediate AsmOperandClass definitions.
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class ImmediateAsmOperand<string predicate, string render="addImmOperands">
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: AsmOperandClass {
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let Name = NAME;
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let PredicateMethod = predicate;
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let RenderMethod = render;
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}
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// Base class for immediate operands with optional encoder.
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class ImmediateOp<ValueType vt, string asmop, int width, bit is_signed = 0,
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string encoder = "", string decoder = ""> : Operand<vt> {
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let PrintMethod = "print"#asmop#"Operand";
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let ParserMatchClass = !cast<AsmOperandClass>(asmop);
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let OperandType = "OPERAND_IMMEDIATE";
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// Set decoder method based on signedness if not explicitly provided
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let DecoderMethod = !if(!eq(decoder, ""),
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!if(is_signed,
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"decodeSImmOperand<"#width#">",
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"decodeUImmOperand<"#width#">"),
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decoder);
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// Set encoder method if provided
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let EncoderMethod = !if(!eq(encoder, ""),
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"",
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"getImmEncoding<" # encoder # ">");
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}
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//===----------------------------------------------------------------------===//
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// Multiclasses for complete immediate definitions
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// (AsmOperand + Operand + ImmLeaf).
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//===----------------------------------------------------------------------===//
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// Helper multiclass that generates operand + patterns together while keeping
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// them as separate definitions for GlobalISel compatibility.
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multiclass ImmOpWithPatterns<ValueType vt, string asmop, int width,
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bit is_signed, code pred, SDNodeXForm xform,
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string encoder = ""> {
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// Operand definition (for instruction operands)
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def "" : ImmediateOp<vt, asmop, width, is_signed, encoder>;
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// ImmLeaf for imm nodes (for DAG pattern matching)
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def _pat : ImmLeaf<vt, pred, xform>;
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// TImmLeaf for timm nodes (for target-specific pattern matching, e.g., intrinsics)
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def _timm : TImmLeaf<vt, pred, xform>;
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}
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// Creates Operand and separate ImmLeaf definitions for unsigned immediates.
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multiclass UnsignedImmediate<ValueType vt, code pred, SDNodeXForm xform,
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string asmop, int width, string encoder = "">
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: ImmOpWithPatterns<vt, asmop, width, 0, pred, xform, encoder>;
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// Creates Operand and separate ImmLeaf definitions for signed immediates.
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multiclass SignedImmediate<ValueType vt, code pred, SDNodeXForm xform,
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string asmop, int width, string encoder = "">
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: ImmOpWithPatterns<vt, asmop, width, 1, pred, xform, encoder>;
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// Multiclass for signed immediate operands with both regular and
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// PC-relative versions.
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multiclass SignedImmediateWithPCRel<ValueType vt, code pred,
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SDNodeXForm xform, string asmop,
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int width, string fixup_imm,
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string fixup_pcrel>
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: SignedImmediate<vt, pred, xform, asmop, width, fixup_imm> {
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// PC-relative immediate: instantiate SignedImmediate with PC-relative fixup
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defm _pcrel : SignedImmediate<vt, pred, xform, asmop, width, fixup_pcrel>;
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}
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//===----------------------------------------------------------------------===//
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// Immediate AsmOperand definitions
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//===----------------------------------------------------------------------===//
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def U1Imm : ImmediateAsmOperand<"isUImm<1>">;
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def U2Imm : ImmediateAsmOperand<"isUImm<2>">;
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def U3Imm : ImmediateAsmOperand<"isUImm<3>">;
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def U4Imm : ImmediateAsmOperand<"isUImm<4>">;
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def U5Imm : ImmediateAsmOperand<"isUImm<5>">;
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def U6Imm : ImmediateAsmOperand<"isUImm<6>">;
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def U7Imm : ImmediateAsmOperand<"isUImm<7>">;
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def U8Imm : ImmediateAsmOperand<"isUImm<8>">;
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def U10Imm : ImmediateAsmOperand<"isUImm<10>">;
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def U12Imm : ImmediateAsmOperand<"isUImm<12>">;
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def S5Imm : ImmediateAsmOperand<"isSImm<5>">;
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// Special cases that have custom predicat and/or render method.
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def ATBitsAsHint : ImmediateAsmOperand<"isATBitsAsHint">; //Predicate always fails.
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def ImmZero : ImmediateAsmOperand<"isImmZero">;
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def U16Imm : ImmediateAsmOperand<"isU16Imm","addU16ImmOperands">;
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def S16Imm : ImmediateAsmOperand<"isS16Imm","addS16ImmOperands">;
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def S17Imm : ImmediateAsmOperand<"isS17Imm","addS16ImmOperands">;
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def S32Imm : ImmediateAsmOperand<"isS32Imm">;
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def S34Imm : ImmediateAsmOperand<"isS34Imm">;
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//===----------------------------------------------------------------------===//
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// i32 immediate operands
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//===----------------------------------------------------------------------===//
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defm u1imm : UnsignedImmediate<i32,
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[{ return isUInt<1>(Imm); }], NOOP_SDNodeXForm,
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"U1Imm", 1>;
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defm u2imm : UnsignedImmediate<i32,
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[{ return isUInt<2>(Imm); }], NOOP_SDNodeXForm,
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"U2Imm", 2>;
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defm u3imm : UnsignedImmediate<i32,
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[{ return isUInt<3>(Imm); }], NOOP_SDNodeXForm,
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"U3Imm", 3>;
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defm u4imm : UnsignedImmediate<i32,
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[{ return isUInt<4>(Imm); }], NOOP_SDNodeXForm,
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"U4Imm", 4>;
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defm u5imm : UnsignedImmediate<i32,
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[{ return isUInt<5>(Imm); }], NOOP_SDNodeXForm,
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"U5Imm", 5>;
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defm u6imm : UnsignedImmediate<i32,
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[{ return isUInt<6>(Imm); }], NOOP_SDNodeXForm,
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"U6Imm", 6>;
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defm u7imm : UnsignedImmediate<i32,
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[{ return isUInt<7>(Imm); }], NOOP_SDNodeXForm,
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"U7Imm", 7>;
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defm u8imm : UnsignedImmediate<i32,
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[{ return isUInt<8>(Imm); }], NOOP_SDNodeXForm,
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"U8Imm", 8>;
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defm u10imm : UnsignedImmediate<i32,
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[{ return isUInt<10>(Imm); }], NOOP_SDNodeXForm,
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"U10Imm", 10>;
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defm u12imm : UnsignedImmediate<i32,
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[{ return isUInt<12>(Imm); }], NOOP_SDNodeXForm,
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"U12Imm", 12>;
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defm s5imm : SignedImmediate<i32,
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[{ return isInt<5>(Imm); }], NOOP_SDNodeXForm,
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"S5Imm", 5>;
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defm s32imm : SignedImmediateWithPCRel<i32,
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[{ return isInt<34>(Imm); }], NOOP_SDNodeXForm,
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"S34Imm", 34, "PPC::fixup_ppc_imm32", "PPC::fixup_ppc_pcrel32">;
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defm s34imm : SignedImmediate<i32,
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[{ return isInt<34>(Imm); }], NOOP_SDNodeXForm,
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"S34Imm", 34, "PPC::fixup_ppc_imm34">;
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//===----------------------------------------------------------------------===//
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// i64 immediate operands
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//===----------------------------------------------------------------------===//
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defm s32imm64 : SignedImmediateWithPCRel<i64,
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[{ return isInt<32>(Imm); }], NOOP_SDNodeXForm,
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"S32Imm", 32, "PPC::fixup_ppc_imm32", "PPC::fixup_ppc_pcrel32">;
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defm s34imm64 : SignedImmediateWithPCRel<i64,
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[{ return isInt<34>(Imm); }], NOOP_SDNodeXForm,
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"S34Imm", 34, "PPC::fixup_ppc_imm34", "PPC::fixup_ppc_pcrel34">;
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//===----------------------------------------------------------------------===//
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// Special case immediate operands
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//===----------------------------------------------------------------------===//
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// immZero represents a hardcoded zero register encoding, it is NOT used in DAG
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// patterns. It is only used as an instruction operand for assembly/disassembly,
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// specifically to represent a hardcoded zero register value in PC-relative
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// addressing modes.
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def immZero : Operand<i32> {
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let PrintMethod = "printImmZeroOperand";
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let ParserMatchClass = ImmZero;
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let DecoderMethod = "decodeImmZeroOperand";
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let OperandType = "OPERAND_IMMEDIATE";
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}
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// atimm is used to represent branch prediction hints, not a general immediate
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// value. It's a 2-bit AT (Address Translation) field in PPC branch instructions
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// and is an assembly-only operand that prints as `+` or `-` symbols, not
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// numeric values.
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def atimm : Operand<i32> {
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let PrintMethod = "printATBitsAsHint";
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let ParserMatchClass = ATBitsAsHint;
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let OperandType = "OPERAND_IMMEDIATE";
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}
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// Special cases: s16imm and u16imm have custom encoder methods.
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defm s16imm : SignedImmediate<i32,
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[{ return isInt<16>(Imm); }], NOOP_SDNodeXForm,
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"S16Imm", 16, "PPC::fixup_ppc_half16">;
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defm u16imm : UnsignedImmediate<i32,
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[{ return isUInt<16>(Imm); }], NOOP_SDNodeXForm,
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"U16Imm", 16, "PPC::fixup_ppc_half16">;
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// s16imm64 uses imm64SExt16 pattern to match the operand type.
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def s16imm64 : ImmediateOp<i64, "S16Imm", 16, 1, "PPC::fixup_ppc_half16">;
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// u16imm64 uses two different patterns depending on the instruction context:
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// * immZExt16 - For low 16-bit immediates
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// * imm16ShiftedZExt - For high 16-bit immediates (shifted)
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def u16imm64 : ImmediateOp<i64, "U16Imm", 16, 0, "PPC::fixup_ppc_half16">;
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// Special case: s17imm uses S16Imm print method but accepts wider range.
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// This operand type is used for addis/lis to allow the assembler parser
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// to accept immediates in the range -65536..65535 for compatibility
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// with the GNU assembler. The operand is treated as 16-bit otherwise.
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def s17imm : ImmediateOp<i32, "S17Imm", 16, 1, "PPC::fixup_ppc_half16"> {
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let PrintMethod = "printS16ImmOperand";
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}
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def s17imm64 : ImmediateOp<i64, "S17Imm", 16, 1, "PPC::fixup_ppc_half16"> {
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let PrintMethod = "printS16ImmOperand";
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}
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