Csanád Hajdú 4a00c84fbb

[AArch64] Allow register offset addressing mode for prefetch (#124534) ...

Previously instruction selection failed to generate PRFM instructions
with register offsets because `AArch64ISD::PREFETCH` is not a
`MemSDNode`.

2025-01-28 09:16:40 +00:00

..

AArch64

[AArch64] Allow register offset addressing mode for prefetch (#124534)

2025-01-28 09:16:40 +00:00

AMDGPU

[NFC][AMDGPU] Autogenerating test cases (#124507)

2025-01-28 13:41:59 +05:30

ARC

[ARC,test] Change llc -march= to -mtriple=

2024-12-15 12:29:53 -08:00

ARM

[PartiallyInlineLibCalls] Add infrastructure for emitting optimization remarks from PartiallyInlineLibCalls (#122654)

2025-01-22 13:15:40 +07:00

AVR

[AVR] Force relocations for non-encodable jumps (#121498)

2025-01-20 09:23:57 +08:00

BPF

[BPF,test] Change llc -march= to -mtriple=

2024-12-15 11:04:24 -08:00

CSKY

…

DirectX

[HLSL][SPIRV][DXIL] Implement WaveActiveMax intrinsic (#123428)

2025-01-27 23:26:56 -08:00

Generic

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Hexagon

[llvm][CodeGen] Fix the issue caused by live interval checking in window scheduler (#123184)

2025-01-23 09:39:03 +08:00

Inputs

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Lanai

[test] Remove redundant -march= when target triple is specified in IR

2024-12-15 12:42:17 -08:00

LoongArch

[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

2025-01-23 12:49:35 -08:00

M68k

[M68k] Fix llc pass test after 3630d9ef65b30af7e4ca78e668649bbc48b5be66

2025-01-23 08:28:25 -05:00

Mips

[Mips] Add the missing judgment when processing function handleMFLOSlot (#121463)

2025-01-24 20:03:03 +08:00

MIR

[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)

2025-01-23 16:07:57 +01:00

MLRegAlloc

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MSP430

[M68k,MSP430,test] Change llc -march= to -mtriple=

2024-12-15 10:09:30 -08:00

NVPTX

[NVPTX] Add float to tf32 conversion intrinsics (#124316)

2025-01-27 15:52:43 +05:30

PowerPC

[PowerPC] Fix saving of Link Register when using ROP Protect (#123101)

2025-01-22 13:44:20 -05:00

RISCV

[RISCV] Add MIPS extensions (#121394)

2025-01-28 08:04:09 +01:00

SPARC

[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

2025-01-23 12:49:35 -08:00

SPIRV

[HLSL][SPIRV][DXIL] Implement WaveActiveMax intrinsic (#123428)

2025-01-27 23:26:56 -08:00

SystemZ

[MachineSink] Extend loop sinking capability (#117247)

2025-01-23 17:08:23 -08:00

Thumb

[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

2025-01-23 12:49:35 -08:00

Thumb2

Revert "[MachineLICM] Use RegisterClassInfo::getRegPressureSetLimit (#119826)"

2025-01-10 09:05:06 +01:00

VE

[VE,test] Change llc -march= to -mtriple=

2024-12-15 10:24:14 -08:00

WebAssembly

[WebAssembly] Fix catch block type in wasm64 (#124381)

2025-01-27 11:01:48 -08:00

WinCFGuard

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WinEH

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X86

[X86] huge-stack-offset.ll - add gnux32 test coverage

2025-01-27 14:10:16 +00:00

XCore

[XCore,test] Change llc -march= to -mtriple=

2024-12-15 10:31:38 -08:00

Xtensa

[CodeGen] Clean up tests that depend on implicit .text in MCAsmStreamer

2024-12-22 21:11:32 -08:00