shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
Natalie Chouinard 4abe3f18e2 [SPIRV] Fix bug in emitting GLSL ext inst names 
Lookup extended instruction numbers in the given instruction set so that
correct names are now emitted for GLSL.std.450 instructions as well as
OpenCL.std.

Add a single test to verify correct abs intrinsic names are emitted when
targetting logical SPIR-V.

Depends on D156424

Differential Revision: https://reviews.llvm.org/D159227
2023-09-19 13:44:13 +00:00
..
AArch64
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
AMDGPU
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
ARC
…
ARM
Revert "[ARM] Always lower direct calls as direct when the outliner is enabled (#66434)"
2023-09-18 09:45:46 -07:00
AVR
[RA] Split a virtual register in cold blocks if it is not assigned preferred physical register
2023-09-15 19:52:50 +00:00
BPF
Revert "Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size"
2023-09-18 17:24:53 +02:00
CSKY
[CSKY] Optimize multiplication with immediates
2023-08-08 14:13:49 +08:00
DirectX
[DirectX backend] avoid generate redundant bitcast in DXILPrepareModule (#65163)
2023-09-01 20:08:39 -04:00
Generic
[llvm][AArch64] Disable BigByval with expensive checks
2023-08-31 10:15:45 +00:00
Hexagon
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
Inputs
…
Lanai
[test] Change llc -march= to -mtriple= & llvm-mc -arch= to -triple=
2023-09-11 15:11:01 -07:00
LoongArch
[LoongArch] Fix incorrect instruction 'and' in pattern
2023-09-15 16:16:06 +08:00
M68k
[CodeGen] Add machine verification to some tests
2023-07-24 11:04:10 +01:00
Mips
[SDAG][RISCV] Avoid neg instructions when lowering atomic_load_sub with a constant rhs
2023-09-16 17:09:41 +08:00
MIR
[AMDGPU] Add IsChainFunction to the MachineFunctionInfo
2023-08-21 12:37:32 +02:00
MLRegAlloc
[mlgo] Fix regalloc tests
2023-09-15 17:27:34 -04:00
MSP430
…
NVPTX
[NVPTX] Tighten up legal v2i16 ops a bit
2023-09-12 16:10:20 +02:00
PowerPC
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
RISCV
[RISCV] Add tests for memory constraint A
2023-09-19 19:51:04 +08:00
SPARC
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
SPIRV
[SPIRV] Fix bug in emitting GLSL ext inst names
2023-09-19 13:44:13 +00:00
SystemZ
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
Thumb
[Thumb1] Use callee-saved register to adjust stack pointer
2023-08-17 18:29:50 +01:00
Thumb2
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
VE
[DAG] SimplifyDemandedBits - if we're only demanding the msb, a UMIN/UMAX node can be simplified to a AND/OR node respectively.
2023-08-18 12:12:22 +01:00
WebAssembly
[IR] Remove unnecessary bitcast from CreateMalloc()
2023-09-18 14:58:16 +02:00
WinCFGuard
…
WinEH
…
X86
[CodeGen] Renumber slot indexes before register allocation (#66334)
2023-09-19 11:18:12 +01:00
XCore
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00