Guozhi Wei 22e7da9597 [PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0 ...

According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0.

This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified.

Differential Revision: https://reviews.llvm.org/D32880

llvm-svn: 302834

2017-05-11 22:17:35 +00:00

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dcbt.txt

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lit.local.cfg

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ppc64-encoding-4xx.txt

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ppc64-encoding-6xx.txt

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ppc64-encoding-bookII.txt

[PowerPC] Add support for the extended dcbf form and mnemonics

2016-09-02 23:41:54 +00:00

ppc64-encoding-bookIII.txt

Add some Book-E instructions to the asm parser and printer.

2017-01-29 04:55:57 +00:00

ppc64-encoding-e500.txt

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ppc64-encoding-ext.txt

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ppc64-encoding-fp.txt

[PowerPC] Implement missing ISA 2.06 instructions.

2017-01-05 15:00:45 +00:00

ppc64-encoding-p8vector.txt

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ppc64-encoding-p9vector.txt

[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0

2017-05-11 22:17:35 +00:00

ppc64-encoding-vmx.txt

[PPC] add absolute difference altivec instructions and matching intrinsics

2016-10-31 19:47:52 +00:00

ppc64-encoding.txt

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ppc64-operands.txt

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ppc64le-encoding.txt

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qpx.txt

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vsx.txt

[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic

2017-03-15 16:04:53 +00:00