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llvm-project/llvm/test/CodeGen
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David Green 1f01b31755 [AArch64] Extend and regenerate fcvt_combine.ll. NFC 
This adds half and fptoi.sat variants of the tests in fcvt_combine.ll,
and regenerates the resulting check lines.
2021-11-09 20:29:42 +00:00
..
AArch64
[AArch64] Extend and regenerate fcvt_combine.ll. NFC
2021-11-09 20:29:42 +00:00
AMDGPU
AMDGPU: Regenerate test checks
2021-11-09 15:28:59 -05:00
ARC
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ARM
[ARM] implement support for TLS register based stack protector
2021-11-09 18:19:47 +01:00
AVR
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
BPF
BPF: change btf_type_tag BTF output format
2021-11-09 11:34:25 -08:00
CSKY
[CSKY] First patch to construct codegen infra and generate first add instruction
2021-11-01 10:06:56 +08:00
Generic
[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
2021-11-07 15:06:54 +00:00
Hexagon
[Hexagon] Add machine verification to some tests
2021-11-02 15:41:30 +00:00
Inputs
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Lanai
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M68k
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Mips
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
MIR
[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
2021-11-07 15:06:54 +00:00
MSP430
[llvm-readobj] Support dumping of MSP430 ELF attributes
2021-09-28 00:56:11 +03:00
NVPTX
[NVPTX] Mark special registers as reserved
2021-11-03 15:48:04 +03:00
PowerPC
[PowerPC] Implement basic macro fusion in Power10
2021-11-08 17:23:56 +08:00
RISCV
[SelectionDAG] Merge FoldConstantVectorArithmetic into FoldConstantArithmetic (PR36544)
2021-11-09 11:31:01 +00:00
SPARC
[SparcISelLowering] avoid emitting libcalls to __muloti4 and __mulodi4
2021-10-29 13:14:09 -07:00
SystemZ
[SystemZ] Improvement of emitMemMemWrapper()
2021-10-26 17:03:01 +02:00
Thumb
[TwoAddressInstructionPass] Update existing physreg live intervals
2021-11-05 21:20:30 +00:00
Thumb2
[AArch][x86] add tests for vselect; NFC
2021-11-08 15:21:19 -05:00
VE
[VE][NFC] correct bitmasking in popcnt expansion test
2021-10-25 13:55:58 +02:00
WebAssembly
[WebAssembly] Add prototype relaxed float to int trunc instructions
2021-10-28 14:01:53 -07:00
WinCFGuard
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WinEH
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X86
[X86] combineMulToPMADDWD - handle any pow2 vector type and split to legal types
2021-11-09 15:20:43 +00:00
XCore
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