35b685270b
Thus far IntegerType has been signless: a value of IntegerType does not have a sign intrinsically and it's up to the specific operation to decide how to interpret those bits. For example, std.addi does two's complement arithmetic, and std.divis/std.diviu treats the first bit as a sign. This design choice was made some time ago when we did't have lots of dialects and dialects were more rigid. Today we have much more extensible infrastructure and different dialect may want different modelling over integer signedness. So while we can say we want signless integers in the standard dialect, we cannot dictate for others. Requiring each dialect to model the signedness semantics with another set of custom types is duplicating the functionality everywhere, considering the fundamental role integer types play. This CL extends the IntegerType with a signedness semantics bit. This gives each dialect an option to opt in signedness semantics if that's what they want and helps code sharing. The parser is modified to recognize `si[1-9][0-9]*` and `ui[1-9][0-9]*` as signed and unsigned integer types, respectively, leaving the original `i[1-9][0-9]*` to continue to mean no indication over signedness semantics. All existing dialects are not affected (yet) as this is a feature to opt in. More discussions can be found at: https://groups.google.com/a/tensorflow.org/d/msg/mlir/XmkV8HOPWpo/7O4X0Nb_AQAJ Differential Revision: https://reviews.llvm.org/D72533
733 lines
33 KiB
C++
733 lines
33 KiB
C++
//===- LowerGpuOpsToNVVMOps.cpp - MLIR GPU to NVVM lowering passes --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a pass to generate NVVMIR operations for higher-level
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// GPU operations.
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//
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//===----------------------------------------------------------------------===//
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#include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
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#include "mlir/Dialect/GPU/GPUDialect.h"
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#include "mlir/Dialect/LLVMIR/NVVMDialect.h"
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#include "mlir/IR/BlockAndValueMapping.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/DialectConversion.h"
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#include "llvm/Support/FormatVariadic.h"
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#include "../GPUCommon/IndexIntrinsicsOpLowering.h"
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#include "../GPUCommon/OpToFuncCallLowering.h"
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using namespace mlir;
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namespace {
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/// Converts all_reduce op to LLVM/NVVM ops.
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struct GPUAllReduceOpLowering : public ConvertToLLVMPattern {
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using AccumulatorFactory =
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std::function<Value(Location, Value, Value, ConversionPatternRewriter &)>;
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explicit GPUAllReduceOpLowering(LLVMTypeConverter &lowering_)
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: ConvertToLLVMPattern(gpu::AllReduceOp::getOperationName(),
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lowering_.getDialect()->getContext(), lowering_),
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int32Type(LLVM::LLVMType::getInt32Ty(lowering_.getDialect())) {}
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PatternMatchResult
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matchAndRewrite(Operation *op, ArrayRef<Value> operands,
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ConversionPatternRewriter &rewriter) const override {
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Location loc = op->getLoc();
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Value operand = operands.front();
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// TODO(csigg): Generalize to other types of accumulation.
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assert(op->getOperand(0).getType().isSignlessIntOrFloat());
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// Create the reduction using an accumulator factory.
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AccumulatorFactory factory =
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getFactory(cast<gpu::AllReduceOp>(op), operand);
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assert(factory && "failed to create accumulator factory");
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Value result = createBlockReduce(loc, operand, factory, rewriter);
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rewriter.replaceOp(op, {result});
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return matchSuccess();
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}
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private:
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/// Returns an accumulator factory using either the op attribute or the body
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/// region.
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AccumulatorFactory getFactory(gpu::AllReduceOp allReduce,
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Value operand) const {
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if (!allReduce.body().empty()) {
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return getFactory(allReduce.body());
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}
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if (allReduce.op()) {
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auto type = operand.getType().cast<LLVM::LLVMType>();
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return getFactory(*allReduce.op(), type.getUnderlyingType());
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}
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return AccumulatorFactory();
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}
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/// Returns an accumulator factory that clones the body. The body's entry
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/// block is expected to have 2 arguments. The gpu.yield return the
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/// accumulated value of the same type.
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AccumulatorFactory getFactory(Region &body) const {
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return AccumulatorFactory([&](Location loc, Value lhs, Value rhs,
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ConversionPatternRewriter &rewriter) {
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Block *block = rewriter.getInsertionBlock();
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Block *split = rewriter.splitBlock(block, rewriter.getInsertionPoint());
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// Insert accumulator body between split block.
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BlockAndValueMapping mapping;
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mapping.map(body.front().getArgument(0), lhs);
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mapping.map(body.front().getArgument(1), rhs);
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rewriter.cloneRegionBefore(body, *split->getParent(),
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split->getIterator(), mapping);
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// Add branch before inserted body, into body.
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block = block->getNextNode();
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rewriter.create<LLVM::BrOp>(loc, ArrayRef<Value>{},
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llvm::makeArrayRef(block), ValueRange());
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// Replace all gpu.yield ops with branch out of body.
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for (; block != split; block = block->getNextNode()) {
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Operation *terminator = block->getTerminator();
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if (!llvm::isa<gpu::YieldOp>(terminator))
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continue;
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rewriter.setInsertionPointToEnd(block);
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rewriter.replaceOpWithNewOp<LLVM::BrOp>(
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terminator, ArrayRef<Value>{}, llvm::makeArrayRef(split),
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ValueRange(terminator->getOperand(0)));
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}
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// Return accumulator result.
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rewriter.setInsertionPointToStart(split);
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return split->addArgument(lhs.getType());
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});
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}
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/// Returns an accumulator factory that creates an op specified by opName.
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AccumulatorFactory getFactory(StringRef opName, llvm::Type *type) const {
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if (type->isVectorTy() || type->isArrayTy())
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return getFactory(opName, type->getSequentialElementType());
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bool isFloatingPoint = type->isFloatingPointTy();
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if (opName == "add") {
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return isFloatingPoint ? getFactory<LLVM::FAddOp>()
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: getFactory<LLVM::AddOp>();
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}
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if (opName == "mul") {
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return isFloatingPoint ? getFactory<LLVM::FMulOp>()
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: getFactory<LLVM::MulOp>();
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}
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return AccumulatorFactory();
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}
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/// Returns an accumulator factory that creates an op of type T.
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template <typename T> AccumulatorFactory getFactory() const {
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return [](Location loc, Value lhs, Value rhs,
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ConversionPatternRewriter &rewriter) {
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return rewriter.create<T>(loc, lhs.getType(), lhs, rhs);
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};
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}
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/// Creates an all_reduce across the block.
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///
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/// First reduce the elements within a warp. The first thread of each warp
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/// writes the intermediate result to shared memory. After synchronizing the
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/// block, the first warp reduces the values from shared memory. The result
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/// is broadcasted to all threads through shared memory.
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///
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/// %warp_reduce = `createWarpReduce(%operand)`
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/// %shared_mem_ptr = llvm.mlir.addressof @reduce_buffer
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/// %zero = llvm.mlir.constant(0 : i32) : !llvm.i32
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/// %lane_id = nvvm.read.ptx.sreg.laneid : !llvm.i32
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/// %is_first_lane = llvm.icmp "eq" %lane_id, %zero : !llvm.i1
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/// %thread_idx = `getLinearThreadIndex()` : !llvm.i32
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/// llvm.cond_br %is_first_lane, ^then1, ^continue1
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/// ^then1:
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/// %warp_id = `getWarpId()`
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/// %store_dst = llvm.getelementptr %shared_mem_ptr[%zero, %warp_id]
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/// llvm.store %store_dst, %warp_reduce
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/// llvm.br ^continue1
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/// ^continue1:
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/// nvvm.barrier0
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/// %num_warps = `getNumWarps()` : !llvm.i32
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/// %is_valid_warp = llvm.icmp "slt" %thread_idx, %num_warps
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/// %result_ptr = llvm.getelementptr %shared_mem_ptr[%zero, %zero]
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/// llvm.cond_br %is_first_lane, ^then2, ^continue2
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/// ^then2:
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/// %load_src = llvm.getelementptr %shared_mem_ptr[%zero, %thread_idx]
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/// %value = llvm.load %load_src
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/// %result = `createWarpReduce(%value)`
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/// llvm.store %result_ptr, %result
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/// llvm.br ^continue2
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/// ^continue2:
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/// nvvm.barrier0
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/// %result = llvm.load %result_ptr
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/// return %result
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///
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Value createBlockReduce(Location loc, Value operand,
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AccumulatorFactory &accumFactory,
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ConversionPatternRewriter &rewriter) const {
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auto type = operand.getType().cast<LLVM::LLVMType>();
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// Create shared memory array to store the warp reduction.
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auto module = operand.getDefiningOp()->getParentOfType<gpu::GPUModuleOp>();
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assert(module && "op must belong to a module");
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Value sharedMemPtr =
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createSharedMemoryArray(loc, module, type, kWarpSize, rewriter);
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Value zero = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(0u));
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Value laneId = rewriter.create<NVVM::LaneIdOp>(loc, int32Type);
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Value isFirstLane = rewriter.create<LLVM::ICmpOp>(
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loc, LLVM::ICmpPredicate::eq, laneId, zero);
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Value threadIdx = getLinearThreadIndex(loc, rewriter);
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Value blockSize = getBlockSize(loc, rewriter);
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Value activeWidth = getActiveWidth(loc, threadIdx, blockSize, rewriter);
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// Reduce elements within each warp to produce the intermediate results.
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Value warpReduce = createWarpReduce(loc, activeWidth, laneId, operand,
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accumFactory, rewriter);
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// Write the intermediate results to shared memory, using the first lane of
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// each warp.
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createPredicatedBlock(loc, rewriter, isFirstLane, [&] {
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Value warpId = getDivideByWarpSize(threadIdx, rewriter);
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Value storeDst = rewriter.create<LLVM::GEPOp>(
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loc, type, sharedMemPtr, ArrayRef<Value>({zero, warpId}));
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rewriter.create<LLVM::StoreOp>(loc, warpReduce, storeDst);
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});
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rewriter.create<NVVM::Barrier0Op>(loc);
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Value numWarps = getNumWarps(loc, blockSize, rewriter);
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Value isValidWarp = rewriter.create<LLVM::ICmpOp>(
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loc, LLVM::ICmpPredicate::slt, threadIdx, numWarps);
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Value resultPtr = rewriter.create<LLVM::GEPOp>(
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loc, type, sharedMemPtr, ArrayRef<Value>({zero, zero}));
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// Use the first numWarps threads to reduce the intermediate results from
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// shared memory. The final result is written to shared memory again.
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createPredicatedBlock(loc, rewriter, isValidWarp, [&] {
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Value loadSrc = rewriter.create<LLVM::GEPOp>(
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loc, type, sharedMemPtr, ArrayRef<Value>({zero, threadIdx}));
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Value value = rewriter.create<LLVM::LoadOp>(loc, type, loadSrc);
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Value result = createWarpReduce(loc, numWarps, laneId, value,
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accumFactory, rewriter);
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rewriter.create<LLVM::StoreOp>(loc, result, resultPtr);
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});
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rewriter.create<NVVM::Barrier0Op>(loc);
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// Load and return result from shared memory.
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Value result = rewriter.create<LLVM::LoadOp>(loc, type, resultPtr);
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return result;
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}
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/// Creates an if-block skeleton and calls the two factories to generate the
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/// ops in the `then` and `else` block..
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///
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/// llvm.cond_br %condition, ^then, ^continue
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/// ^then:
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/// %then_operands = `thenOpsFactory()`
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/// llvm.br ^continue(%then_operands)
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/// ^else:
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/// %else_operands = `elseOpsFactory()`
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/// llvm.br ^continue(%else_operands)
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/// ^continue(%block_operands):
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///
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template <typename ThenOpsFactory, typename ElseOpsFactory>
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void createIf(Location loc, ConversionPatternRewriter &rewriter,
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Value condition, ThenOpsFactory &&thenOpsFactory,
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ElseOpsFactory &&elseOpsFactory) const {
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Block *currentBlock = rewriter.getInsertionBlock();
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auto currentPoint = rewriter.getInsertionPoint();
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Block *thenBlock = rewriter.splitBlock(currentBlock, currentPoint);
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Block *elseBlock = rewriter.splitBlock(thenBlock, thenBlock->begin());
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Block *continueBlock = rewriter.splitBlock(elseBlock, elseBlock->begin());
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rewriter.setInsertionPointToEnd(currentBlock);
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rewriter.create<LLVM::CondBrOp>(loc, llvm::makeArrayRef(condition),
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ArrayRef<Block *>{thenBlock, elseBlock});
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auto addBranch = [&](ValueRange operands) {
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rewriter.create<LLVM::BrOp>(loc, ArrayRef<Value>{},
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llvm::makeArrayRef(continueBlock),
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llvm::makeArrayRef(operands));
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};
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rewriter.setInsertionPointToStart(thenBlock);
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auto thenOperands = thenOpsFactory();
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addBranch(thenOperands);
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rewriter.setInsertionPointToStart(elseBlock);
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auto elseOperands = elseOpsFactory();
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addBranch(elseOperands);
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assert(thenOperands.size() == elseOperands.size());
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rewriter.setInsertionPointToStart(continueBlock);
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for (auto operand : thenOperands)
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continueBlock->addArgument(operand.getType());
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}
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/// Shortcut for createIf with empty else block and no block operands.
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template <typename Factory>
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void createPredicatedBlock(Location loc, ConversionPatternRewriter &rewriter,
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Value condition,
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Factory &&predicatedOpsFactory) const {
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createIf(
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loc, rewriter, condition,
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[&] {
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predicatedOpsFactory();
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return ArrayRef<Value>();
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},
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[&] { return ArrayRef<Value>(); });
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}
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/// Creates a reduction across the first activeWidth lanes of a warp.
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/// The first lane returns the result, all others return values are undefined.
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Value createWarpReduce(Location loc, Value activeWidth, Value laneId,
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Value operand, AccumulatorFactory accumFactory,
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ConversionPatternRewriter &rewriter) const {
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Value warpSize = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(kWarpSize));
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Value isPartialWarp = rewriter.create<LLVM::ICmpOp>(
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loc, LLVM::ICmpPredicate::slt, activeWidth, warpSize);
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auto type = operand.getType().cast<LLVM::LLVMType>();
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createIf(
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loc, rewriter, isPartialWarp,
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// Generate reduction over a (potentially) partial warp.
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[&] {
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Value value = operand;
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Value one = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(1));
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// Bit mask of active lanes: `(1 << activeWidth) - 1`.
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Value activeMask = rewriter.create<LLVM::SubOp>(
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loc, int32Type,
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rewriter.create<LLVM::ShlOp>(loc, int32Type, one, activeWidth),
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one);
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// Clamp lane: `activeWidth - 1`
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Value maskAndClamp =
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rewriter.create<LLVM::SubOp>(loc, int32Type, activeWidth, one);
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auto dialect = typeConverter.getDialect();
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auto predTy = LLVM::LLVMType::getInt1Ty(dialect);
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auto shflTy = LLVM::LLVMType::getStructTy(dialect, {type, predTy});
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auto returnValueAndIsValidAttr = rewriter.getUnitAttr();
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// Repeatedly shuffle value from 'laneId ^ i' and accumulate if source
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// lane is within the active range. All lanes contain the final
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// result, but only the first lane's result is used.
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for (int i = 1; i < kWarpSize; i <<= 1) {
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Value offset = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(i));
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Value shfl = rewriter.create<NVVM::ShflBflyOp>(
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loc, shflTy, activeMask, value, offset, maskAndClamp,
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returnValueAndIsValidAttr);
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Value isActiveSrcLane = rewriter.create<LLVM::ExtractValueOp>(
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loc, predTy, shfl, rewriter.getIndexArrayAttr(1));
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// Skip the accumulation if the shuffle op read from a lane outside
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// of the active range.
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createIf(
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loc, rewriter, isActiveSrcLane,
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[&] {
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Value shflValue = rewriter.create<LLVM::ExtractValueOp>(
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loc, type, shfl, rewriter.getIndexArrayAttr(0));
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return SmallVector<Value, 1>{
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accumFactory(loc, value, shflValue, rewriter)};
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},
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[&] { return llvm::makeArrayRef(value); });
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value = rewriter.getInsertionBlock()->getArgument(0);
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}
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return SmallVector<Value, 1>{value};
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},
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// Generate a reduction over the entire warp. This is a specialization
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// of the above reduction with unconditional accumulation.
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[&] {
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Value value = operand;
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Value activeMask = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(~0u));
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Value maskAndClamp = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(kWarpSize - 1));
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for (int i = 1; i < kWarpSize; i <<= 1) {
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Value offset = rewriter.create<LLVM::ConstantOp>(
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loc, int32Type, rewriter.getI32IntegerAttr(i));
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Value shflValue = rewriter.create<NVVM::ShflBflyOp>(
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loc, type, activeMask, value, offset, maskAndClamp,
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/*return_value_and_is_valid=*/UnitAttr());
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value = accumFactory(loc, value, shflValue, rewriter);
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}
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return SmallVector<Value, 1>{value};
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});
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return rewriter.getInsertionBlock()->getArgument(0);
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}
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/// Creates a global array stored in shared memory.
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Value createSharedMemoryArray(Location loc, gpu::GPUModuleOp module,
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LLVM::LLVMType elementType, int numElements,
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ConversionPatternRewriter &rewriter) const {
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OpBuilder builder(module.body());
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auto arrayType = LLVM::LLVMType::getArrayTy(elementType, numElements);
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StringRef name = "reduce_buffer";
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auto globalOp = builder.create<LLVM::GlobalOp>(
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loc, arrayType.cast<LLVM::LLVMType>(),
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/*isConstant=*/false, LLVM::Linkage::Internal, name,
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/*value=*/Attribute(), gpu::GPUDialect::getWorkgroupAddressSpace());
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return rewriter.create<LLVM::AddressOfOp>(loc, globalOp);
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}
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/// Returns the index of the thread within the block.
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Value getLinearThreadIndex(Location loc,
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ConversionPatternRewriter &rewriter) const {
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Value dimX = rewriter.create<NVVM::BlockDimXOp>(loc, int32Type);
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Value dimY = rewriter.create<NVVM::BlockDimYOp>(loc, int32Type);
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Value idX = rewriter.create<NVVM::ThreadIdXOp>(loc, int32Type);
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Value idY = rewriter.create<NVVM::ThreadIdYOp>(loc, int32Type);
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Value idZ = rewriter.create<NVVM::ThreadIdZOp>(loc, int32Type);
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Value tmp1 = rewriter.create<LLVM::MulOp>(loc, int32Type, idZ, dimY);
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Value tmp2 = rewriter.create<LLVM::AddOp>(loc, int32Type, tmp1, idY);
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Value tmp3 = rewriter.create<LLVM::MulOp>(loc, int32Type, tmp2, dimX);
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return rewriter.create<LLVM::AddOp>(loc, int32Type, tmp3, idX);
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}
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/// Returns the number of threads in the block.
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Value getBlockSize(Location loc, ConversionPatternRewriter &rewriter) const {
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Value dimX = rewriter.create<NVVM::BlockDimXOp>(loc, int32Type);
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Value dimY = rewriter.create<NVVM::BlockDimYOp>(loc, int32Type);
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Value dimZ = rewriter.create<NVVM::BlockDimZOp>(loc, int32Type);
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Value dimXY = rewriter.create<LLVM::MulOp>(loc, int32Type, dimX, dimY);
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return rewriter.create<LLVM::MulOp>(loc, int32Type, dimXY, dimZ);
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}
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/// Returns the number of warps in the block.
|
|
Value getNumWarps(Location loc, Value blockSize,
|
|
ConversionPatternRewriter &rewriter) const {
|
|
auto warpSizeMinusOne = rewriter.create<LLVM::ConstantOp>(
|
|
loc, int32Type, rewriter.getI32IntegerAttr(kWarpSize - 1));
|
|
auto biasedBlockSize = rewriter.create<LLVM::AddOp>(
|
|
loc, int32Type, blockSize, warpSizeMinusOne);
|
|
return getDivideByWarpSize(biasedBlockSize, rewriter);
|
|
}
|
|
|
|
/// Returns the number of active threads in the warp, not clamped to 32.
|
|
Value getActiveWidth(Location loc, Value threadIdx, Value blockSize,
|
|
ConversionPatternRewriter &rewriter) const {
|
|
Value threadIdxMask = rewriter.create<LLVM::ConstantOp>(
|
|
loc, int32Type, rewriter.getI32IntegerAttr(~(kWarpSize - 1)));
|
|
Value numThreadsWithSmallerWarpId =
|
|
rewriter.create<LLVM::AndOp>(loc, threadIdx, threadIdxMask);
|
|
return rewriter.create<LLVM::SubOp>(loc, blockSize,
|
|
numThreadsWithSmallerWarpId);
|
|
}
|
|
|
|
/// Returns value divided by the warp size (i.e. 32).
|
|
Value getDivideByWarpSize(Value value,
|
|
ConversionPatternRewriter &rewriter) const {
|
|
auto loc = value.getLoc();
|
|
auto warpSize = rewriter.create<LLVM::ConstantOp>(
|
|
loc, int32Type, rewriter.getI32IntegerAttr(kWarpSize));
|
|
return rewriter.create<LLVM::SDivOp>(loc, int32Type, value, warpSize);
|
|
}
|
|
|
|
LLVM::LLVMType int32Type;
|
|
|
|
static constexpr int kWarpSize = 32;
|
|
};
|
|
|
|
struct GPUShuffleOpLowering : public ConvertToLLVMPattern {
|
|
explicit GPUShuffleOpLowering(LLVMTypeConverter &lowering_)
|
|
: ConvertToLLVMPattern(gpu::ShuffleOp::getOperationName(),
|
|
lowering_.getDialect()->getContext(), lowering_) {}
|
|
|
|
/// Lowers a shuffle to the corresponding NVVM op.
|
|
///
|
|
/// Convert the `width` argument into an activeMask (a bitmask which specifies
|
|
/// which threads participate in the shuffle) and a maskAndClamp (specifying
|
|
/// the highest lane which participates in the shuffle).
|
|
///
|
|
/// %one = llvm.constant(1 : i32) : !llvm.i32
|
|
/// %shl = llvm.shl %one, %width : !llvm.i32
|
|
/// %active_mask = llvm.sub %shl, %one : !llvm.i32
|
|
/// %mask_and_clamp = llvm.sub %width, %one : !llvm.i32
|
|
/// %shfl = nvvm.shfl.sync.bfly %active_mask, %value, %offset,
|
|
/// %mask_and_clamp : !llvm<"{ float, i1 }">
|
|
/// %shfl_value = llvm.extractvalue %shfl[0 : index] :
|
|
/// !llvm<"{ float, i1 }">
|
|
/// %shfl_pred = llvm.extractvalue %shfl[1 : index] :
|
|
/// !llvm<"{ float, i1 }">
|
|
PatternMatchResult
|
|
matchAndRewrite(Operation *op, ArrayRef<Value> operands,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
Location loc = op->getLoc();
|
|
gpu::ShuffleOpOperandAdaptor adaptor(operands);
|
|
|
|
auto dialect = typeConverter.getDialect();
|
|
auto valueTy = adaptor.value().getType().cast<LLVM::LLVMType>();
|
|
auto int32Type = LLVM::LLVMType::getInt32Ty(dialect);
|
|
auto predTy = LLVM::LLVMType::getInt1Ty(dialect);
|
|
auto resultTy = LLVM::LLVMType::getStructTy(dialect, {valueTy, predTy});
|
|
|
|
Value one = rewriter.create<LLVM::ConstantOp>(
|
|
loc, int32Type, rewriter.getI32IntegerAttr(1));
|
|
// Bit mask of active lanes: `(1 << activeWidth) - 1`.
|
|
Value activeMask = rewriter.create<LLVM::SubOp>(
|
|
loc, int32Type,
|
|
rewriter.create<LLVM::ShlOp>(loc, int32Type, one, adaptor.width()),
|
|
one);
|
|
// Clamp lane: `activeWidth - 1`
|
|
Value maskAndClamp =
|
|
rewriter.create<LLVM::SubOp>(loc, int32Type, adaptor.width(), one);
|
|
|
|
auto returnValueAndIsValidAttr = rewriter.getUnitAttr();
|
|
Value shfl = rewriter.create<NVVM::ShflBflyOp>(
|
|
loc, resultTy, activeMask, adaptor.value(), adaptor.offset(),
|
|
maskAndClamp, returnValueAndIsValidAttr);
|
|
Value shflValue = rewriter.create<LLVM::ExtractValueOp>(
|
|
loc, valueTy, shfl, rewriter.getIndexArrayAttr(0));
|
|
Value isActiveSrcLane = rewriter.create<LLVM::ExtractValueOp>(
|
|
loc, predTy, shfl, rewriter.getIndexArrayAttr(1));
|
|
|
|
rewriter.replaceOp(op, {shflValue, isActiveSrcLane});
|
|
return matchSuccess();
|
|
}
|
|
};
|
|
|
|
struct GPUFuncOpLowering : ConvertToLLVMPattern {
|
|
explicit GPUFuncOpLowering(LLVMTypeConverter &typeConverter)
|
|
: ConvertToLLVMPattern(gpu::GPUFuncOp::getOperationName(),
|
|
typeConverter.getDialect()->getContext(),
|
|
typeConverter) {}
|
|
|
|
PatternMatchResult
|
|
matchAndRewrite(Operation *op, ArrayRef<Value> operands,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
assert(operands.empty() && "func op is not expected to have operands");
|
|
auto gpuFuncOp = cast<gpu::GPUFuncOp>(op);
|
|
Location loc = gpuFuncOp.getLoc();
|
|
|
|
SmallVector<LLVM::GlobalOp, 3> workgroupBuffers;
|
|
workgroupBuffers.reserve(gpuFuncOp.getNumWorkgroupAttributions());
|
|
for (auto en : llvm::enumerate(gpuFuncOp.getWorkgroupAttributions())) {
|
|
Value attribution = en.value();
|
|
|
|
auto type = attribution.getType().dyn_cast<MemRefType>();
|
|
assert(type && type.hasStaticShape() && "unexpected type in attribution");
|
|
|
|
uint64_t numElements = type.getNumElements();
|
|
|
|
auto elementType = typeConverter.convertType(type.getElementType())
|
|
.cast<LLVM::LLVMType>();
|
|
auto arrayType = LLVM::LLVMType::getArrayTy(elementType, numElements);
|
|
std::string name = std::string(
|
|
llvm::formatv("__wg_{0}_{1}", gpuFuncOp.getName(), en.index()));
|
|
auto globalOp = rewriter.create<LLVM::GlobalOp>(
|
|
gpuFuncOp.getLoc(), arrayType, /*isConstant=*/false,
|
|
LLVM::Linkage::Internal, name, /*value=*/Attribute(),
|
|
gpu::GPUDialect::getWorkgroupAddressSpace());
|
|
workgroupBuffers.push_back(globalOp);
|
|
}
|
|
|
|
// Rewrite the original GPU function to an LLVM function.
|
|
auto funcType = typeConverter.convertType(gpuFuncOp.getType())
|
|
.cast<LLVM::LLVMType>()
|
|
.getPointerElementTy();
|
|
|
|
// Remap proper input types.
|
|
TypeConverter::SignatureConversion signatureConversion(
|
|
gpuFuncOp.front().getNumArguments());
|
|
typeConverter.convertFunctionSignature(
|
|
gpuFuncOp.getType(), /*isVariadic=*/false, signatureConversion);
|
|
|
|
// Create the new function operation. Only copy those attributes that are
|
|
// not specific to function modeling.
|
|
SmallVector<NamedAttribute, 4> attributes;
|
|
for (const auto &attr : gpuFuncOp.getAttrs()) {
|
|
if (attr.first.is(SymbolTable::getSymbolAttrName()) ||
|
|
attr.first.is(impl::getTypeAttrName()) ||
|
|
attr.first.is(gpu::GPUFuncOp::getNumWorkgroupAttributionsAttrName()))
|
|
continue;
|
|
attributes.push_back(attr);
|
|
}
|
|
auto llvmFuncOp = rewriter.create<LLVM::LLVMFuncOp>(
|
|
gpuFuncOp.getLoc(), gpuFuncOp.getName(), funcType,
|
|
LLVM::Linkage::External, attributes);
|
|
|
|
{
|
|
// Insert operations that correspond to converted workgroup and private
|
|
// memory attributions to the body of the function. This must operate on
|
|
// the original function, before the body region is inlined in the new
|
|
// function to maintain the relation between block arguments and the
|
|
// parent operation that assigns their semantics.
|
|
OpBuilder::InsertionGuard guard(rewriter);
|
|
|
|
// Rewrite workgroup memory attributions to addresses of global buffers.
|
|
rewriter.setInsertionPointToStart(&gpuFuncOp.front());
|
|
unsigned numProperArguments = gpuFuncOp.getNumArguments();
|
|
auto i32Type = LLVM::LLVMType::getInt32Ty(typeConverter.getDialect());
|
|
|
|
Value zero = nullptr;
|
|
if (!workgroupBuffers.empty())
|
|
zero = rewriter.create<LLVM::ConstantOp>(loc, i32Type,
|
|
rewriter.getI32IntegerAttr(0));
|
|
for (auto en : llvm::enumerate(workgroupBuffers)) {
|
|
LLVM::GlobalOp global = en.value();
|
|
Value address = rewriter.create<LLVM::AddressOfOp>(loc, global);
|
|
auto elementType = global.getType().getArrayElementType();
|
|
Value memory = rewriter.create<LLVM::GEPOp>(
|
|
loc, elementType.getPointerTo(global.addr_space().getZExtValue()),
|
|
address, ArrayRef<Value>{zero, zero});
|
|
|
|
// Build a memref descriptor pointing to the buffer to plug with the
|
|
// existing memref infrastructure. This may use more registers than
|
|
// otherwise necessary given that memref sizes are fixed, but we can try
|
|
// and canonicalize that away later.
|
|
Value attribution = gpuFuncOp.getWorkgroupAttributions()[en.index()];
|
|
auto type = attribution.getType().cast<MemRefType>();
|
|
auto descr = MemRefDescriptor::fromStaticShape(
|
|
rewriter, loc, typeConverter, type, memory);
|
|
signatureConversion.remapInput(numProperArguments + en.index(), descr);
|
|
}
|
|
|
|
// Rewrite private memory attributions to alloca'ed buffers.
|
|
unsigned numWorkgroupAttributions =
|
|
gpuFuncOp.getNumWorkgroupAttributions();
|
|
auto int64Ty = LLVM::LLVMType::getInt64Ty(typeConverter.getDialect());
|
|
for (auto en : llvm::enumerate(gpuFuncOp.getPrivateAttributions())) {
|
|
Value attribution = en.value();
|
|
auto type = attribution.getType().cast<MemRefType>();
|
|
assert(type && type.hasStaticShape() &&
|
|
"unexpected type in attribution");
|
|
|
|
// Explicitly drop memory space when lowering private memory
|
|
// attributions since NVVM models it as `alloca`s in the default
|
|
// memory space and does not support `alloca`s with addrspace(5).
|
|
auto ptrType = typeConverter.convertType(type.getElementType())
|
|
.cast<LLVM::LLVMType>()
|
|
.getPointerTo();
|
|
Value numElements = rewriter.create<LLVM::ConstantOp>(
|
|
gpuFuncOp.getLoc(), int64Ty,
|
|
rewriter.getI64IntegerAttr(type.getNumElements()));
|
|
Value allocated = rewriter.create<LLVM::AllocaOp>(
|
|
gpuFuncOp.getLoc(), ptrType, numElements, /*alignment=*/0);
|
|
auto descr = MemRefDescriptor::fromStaticShape(
|
|
rewriter, loc, typeConverter, type, allocated);
|
|
signatureConversion.remapInput(
|
|
numProperArguments + numWorkgroupAttributions + en.index(), descr);
|
|
}
|
|
}
|
|
|
|
// Move the region to the new function, update the entry block signature.
|
|
rewriter.inlineRegionBefore(gpuFuncOp.getBody(), llvmFuncOp.getBody(),
|
|
llvmFuncOp.end());
|
|
rewriter.applySignatureConversion(&llvmFuncOp.getBody(),
|
|
signatureConversion);
|
|
|
|
rewriter.eraseOp(gpuFuncOp);
|
|
return matchSuccess();
|
|
}
|
|
};
|
|
|
|
struct GPUReturnOpLowering : public ConvertToLLVMPattern {
|
|
GPUReturnOpLowering(LLVMTypeConverter &typeConverter)
|
|
: ConvertToLLVMPattern(gpu::ReturnOp::getOperationName(),
|
|
typeConverter.getDialect()->getContext(),
|
|
typeConverter) {}
|
|
|
|
PatternMatchResult
|
|
matchAndRewrite(Operation *op, ArrayRef<Value> operands,
|
|
ConversionPatternRewriter &rewriter) const override {
|
|
rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(op, operands,
|
|
ArrayRef<Block *>());
|
|
return matchSuccess();
|
|
}
|
|
};
|
|
|
|
/// Import the GPU Ops to NVVM Patterns.
|
|
#include "GPUToNVVM.cpp.inc"
|
|
|
|
/// A pass that replaces all occurrences of GPU device operations with their
|
|
/// corresponding NVVM equivalent.
|
|
///
|
|
/// This pass only handles device code and is not meant to be run on GPU host
|
|
/// code.
|
|
class LowerGpuOpsToNVVMOpsPass
|
|
: public OperationPass<LowerGpuOpsToNVVMOpsPass, gpu::GPUModuleOp> {
|
|
public:
|
|
void runOnOperation() override {
|
|
gpu::GPUModuleOp m = getOperation();
|
|
|
|
/// MemRef conversion for GPU to NVVM lowering. The GPU dialect uses memory
|
|
/// space 5 for private memory attributions, but NVVM represents private
|
|
/// memory allocations as local `alloca`s in the default address space. This
|
|
/// converter drops the private memory space to support the use case above.
|
|
LLVMTypeConverter converter(m.getContext());
|
|
converter.addConversion([&](MemRefType type) -> Optional<Type> {
|
|
if (type.getMemorySpace() != gpu::GPUDialect::getPrivateAddressSpace())
|
|
return llvm::None;
|
|
return converter.convertType(MemRefType::Builder(type).setMemorySpace(0));
|
|
});
|
|
|
|
OwningRewritePatternList patterns;
|
|
populateStdToLLVMConversionPatterns(converter, patterns);
|
|
populateGpuToNVVMConversionPatterns(converter, patterns);
|
|
ConversionTarget target(getContext());
|
|
target.addIllegalDialect<gpu::GPUDialect>();
|
|
target.addIllegalOp<LLVM::FAbsOp, LLVM::FCeilOp, LLVM::CosOp,
|
|
LLVM::ExpOp>();
|
|
target.addIllegalOp<FuncOp>();
|
|
target.addLegalDialect<LLVM::LLVMDialect>();
|
|
target.addLegalDialect<NVVM::NVVMDialect>();
|
|
target.addDynamicallyLegalOp<mlir::LLVM::CallOp>(
|
|
gpu::filterIllegalLLVMIntrinsics({"tanh", "tanhf"}, m.getContext()));
|
|
// TODO(csigg): Remove once we support replacing non-root ops.
|
|
target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>();
|
|
if (failed(applyPartialConversion(m, target, patterns, &converter)))
|
|
signalPassFailure();
|
|
}
|
|
};
|
|
|
|
} // anonymous namespace
|
|
|
|
void mlir::populateGpuToNVVMConversionPatterns(
|
|
LLVMTypeConverter &converter, OwningRewritePatternList &patterns) {
|
|
populateWithGenerated(converter.getDialect()->getContext(), &patterns);
|
|
patterns
|
|
.insert<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, NVVM::ThreadIdXOp,
|
|
NVVM::ThreadIdYOp, NVVM::ThreadIdZOp>,
|
|
GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, NVVM::BlockDimXOp,
|
|
NVVM::BlockDimYOp, NVVM::BlockDimZOp>,
|
|
GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, NVVM::BlockIdXOp,
|
|
NVVM::BlockIdYOp, NVVM::BlockIdZOp>,
|
|
GPUIndexIntrinsicOpLowering<gpu::GridDimOp, NVVM::GridDimXOp,
|
|
NVVM::GridDimYOp, NVVM::GridDimZOp>,
|
|
GPUAllReduceOpLowering, GPUShuffleOpLowering, GPUFuncOpLowering,
|
|
GPUReturnOpLowering>(converter);
|
|
patterns.insert<OpToFuncCallLowering<AbsFOp>>(converter, "__nv_fabsf",
|
|
"__nv_fabs");
|
|
patterns.insert<OpToFuncCallLowering<CeilFOp>>(converter, "__nv_ceilf",
|
|
"__nv_ceil");
|
|
patterns.insert<OpToFuncCallLowering<CosOp>>(converter, "__nv_cosf",
|
|
"__nv_cos");
|
|
patterns.insert<OpToFuncCallLowering<ExpOp>>(converter, "__nv_expf",
|
|
"__nv_exp");
|
|
patterns.insert<OpToFuncCallLowering<TanhOp>>(converter, "__nv_tanhf",
|
|
"__nv_tanh");
|
|
}
|
|
|
|
std::unique_ptr<OpPassBase<gpu::GPUModuleOp>>
|
|
mlir::createLowerGpuOpsToNVVMOpsPass() {
|
|
return std::make_unique<LowerGpuOpsToNVVMOpsPass>();
|
|
}
|
|
|
|
static PassRegistration<LowerGpuOpsToNVVMOpsPass>
|
|
pass("convert-gpu-to-nvvm", "Generate NVVM operations for gpu operations");
|