Luke Lau f43ad88ae1

[RISCV] Handle zvfhmin and zvfbfmin promotion to f32 in half arith costs (#108361) ...

Arithmetic half or bfloat ops on zvfhmin and zvfbfmin respectively will
be promoted and carried out in f32, so this updates
getArithmeticInstrCost to check for this.

2024-09-25 18:50:16 +08:00

..

AArch64

[AArch64][CostModel] Reduce the cost of fadd reduction with fast flag (#108791)

2024-09-24 14:35:01 +05:30

AMDGPU

AMDGPU: Correct costs of saturating add/sub intrinsics (#100808)

2024-08-09 12:55:15 +04:00

ARM

TTI: Check legalization cost of add/sub overflow ISD nodes (#100518)

2024-08-08 23:44:07 +04:00

PowerPC

[PowerPC] adjust cost for extract i64 from vector on P9 and above (#82963)

2024-03-04 09:37:11 +08:00

RISCV

[RISCV] Handle zvfhmin and zvfbfmin promotion to f32 in half arith costs (#108361)

2024-09-25 18:50:16 +08:00

SystemZ

[SystemZ] Add custom handling of legal vectors with reduce-add. (#88495)

2024-04-12 18:05:30 +02:00

X86

[LV] Assign cost to all interleave members when not interleaving.

2024-09-11 21:04:34 +01:00

free-intrinsics-datalayout.ll

[CostModel] No cost for llvm.allow.{runtime,ubsan}.check() (#86064)

2024-03-31 22:27:57 -07:00

free-intrinsics-no_info.ll

[CostModel] No cost for llvm.allow.{runtime,ubsan}.check() (#86064)

2024-03-31 22:27:57 -07:00

no_info.ll

[CostModel] Convert some tests to opaque pointers (NFC)

2022-12-15 09:50:34 +01:00