808cd69a92
Instead of flat schedules, we now use so-called schedule trees to represent the execution order of the statements in a SCoP. Schedule trees make it a lot easier to analyze, understand and modify properties of a schedule, as specific nodes in the tree can be choosen and possibly replaced. This patch does not yet fully move our DependenceInfo pass to schedule trees, as some additional performance analysis is needed here. (In general schedule trees should be faster in compile-time, as the more structured representation is generally easier to analyze and work with). We also can not yet perform the reduction analysis on schedule trees. For more information regarding schedule trees, please see Section 6 of https://lirias.kuleuven.be/handle/123456789/497238 llvm-svn: 242130
138 lines
4.0 KiB
LLVM
138 lines
4.0 KiB
LLVM
; RUN: opt %loadPolly -polly-detect-unprofitable -polly-no-early-exit -polly-ast -analyze < %s | FileCheck %s
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;#include <string.h>
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;#define N 1024
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;
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;int A[N];
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;
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;void sequential_loops() {
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; int i;
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; for (i = 0; i < N/2; i++) {
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; A[i] = 1;
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; }
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; for (i = N/2 ; i < N; i++) {
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; A[i] = 2;
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; }
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;}
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;
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;int main () {
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; int i;
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; memset(A, 0, sizeof(int) * N);
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;
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; sequential_loops();
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;
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; for (i = 0; i < N; i++) {
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; if (A[i] != 1 && i < N/2)
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; return 1;
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; if (A[i] != 2 && i >= N/2)
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; return 1;
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; }
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;
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; return 0;
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;}
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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@A = common global [1024 x i32] zeroinitializer, align 4 ; <[1024 x i32]*> [#uses=5]
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define void @sequential_loops() nounwind {
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bb:
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br label %bb1
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bb1: ; preds = %bb3, %bb
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%indvar1 = phi i64 [ %indvar.next2, %bb3 ], [ 0, %bb ]
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%scevgep4 = getelementptr [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvar1
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%exitcond3 = icmp ne i64 %indvar1, 512
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br i1 %exitcond3, label %bb2, label %bb4
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bb2: ; preds = %bb1
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store i32 1, i32* %scevgep4
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br label %bb3
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bb3: ; preds = %bb2
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%indvar.next2 = add i64 %indvar1, 1
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br label %bb1
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bb4: ; preds = %bb1
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br label %bb5
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bb5: ; preds = %bb7, %bb4
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%indvar = phi i64 [ %indvar.next, %bb7 ], [ 0, %bb4 ]
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%tmp = add i64 %indvar, 512
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%scevgep = getelementptr [1024 x i32], [1024 x i32]* @A, i64 0, i64 %tmp
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%exitcond = icmp ne i64 %indvar, 512
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br i1 %exitcond, label %bb6, label %bb8
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bb6: ; preds = %bb5
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store i32 2, i32* %scevgep
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br label %bb7
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bb7: ; preds = %bb6
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%indvar.next = add i64 %indvar, 1
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br label %bb5
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bb8: ; preds = %bb5
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ret void
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}
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define i32 @main() nounwind {
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bb:
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call void @llvm.memset.p0i8.i64(i8* bitcast ([1024 x i32]* @A to i8*), i8 0, i64 4096, i32 1, i1 false)
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call void @sequential_loops()
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br label %bb1
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bb1: ; preds = %bb15, %bb
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%indvar = phi i64 [ %indvar.next, %bb15 ], [ 0, %bb ]
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%i.0 = trunc i64 %indvar to i32
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%scevgep = getelementptr [1024 x i32], [1024 x i32]* @A, i64 0, i64 %indvar
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%tmp = icmp slt i32 %i.0, 1024
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br i1 %tmp, label %bb2, label %bb16
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bb2: ; preds = %bb1
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%tmp3 = load i32, i32* %scevgep
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%tmp4 = icmp ne i32 %tmp3, 1
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br i1 %tmp4, label %bb5, label %bb8
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bb5: ; preds = %bb2
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%tmp6 = icmp slt i32 %i.0, 512
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br i1 %tmp6, label %bb7, label %bb8
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bb7: ; preds = %bb5
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br label %bb17
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bb8: ; preds = %bb5, %bb2
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%tmp9 = load i32, i32* %scevgep
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%tmp10 = icmp ne i32 %tmp9, 2
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br i1 %tmp10, label %bb11, label %bb14
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bb11: ; preds = %bb8
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%tmp12 = icmp sge i32 %i.0, 512
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br i1 %tmp12, label %bb13, label %bb14
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bb13: ; preds = %bb11
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br label %bb17
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bb14: ; preds = %bb11, %bb8
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br label %bb15
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bb15: ; preds = %bb14
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%indvar.next = add i64 %indvar, 1
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br label %bb1
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bb16: ; preds = %bb1
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br label %bb17
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bb17: ; preds = %bb16, %bb13, %bb7
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%.0 = phi i32 [ 1, %bb7 ], [ 1, %bb13 ], [ 0, %bb16 ]
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ret i32 %.0
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}
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declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind
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; CHECK: {
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; CHECK: for (int c0 = 0; c0 <= 511; c0 += 1)
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; CHECK: Stmt_bb2(c0);
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; CHECK: for (int c0 = 0; c0 <= 511; c0 += 1)
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; CHECK: Stmt_bb6(c0);
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; CHECK: }
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