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llvm-project/llvm/test/CodeGen
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Stanislav Mekhanoshin 4c4b71843b [AMDGPU] Propagate amdgpu-waves-per-eu to callees 
Differential Revision: https://reviews.llvm.org/D76868
2020-03-26 14:43:44 -07:00
..
AArch64
[AArch64][SVE] Implement structured store intrinsics
2020-03-26 09:34:51 +00:00
AMDGPU
[AMDGPU] Propagate amdgpu-waves-per-eu to callees
2020-03-26 14:43:44 -07:00
ARC
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ARM
[ARM] Move ConstantIsland and LowOverheadLoops Passes.
2020-03-25 16:49:21 +01:00
AVR
[AVR] Fix incorrect register state for LDRdPtr
2020-03-03 17:34:54 +08:00
BPF
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
Generic
[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
2020-03-26 14:10:20 -07:00
Hexagon
Revert "Include static prof data when collecting loop BBs"
2020-03-24 09:41:16 -07:00
Inputs
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Lanai
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
Mips
[GlobalISel] combine G_TRUNC with G_MERGE_VALUES
2020-03-16 14:42:01 +01:00
MIR
[AMDGPU] Move frame pointer from s34 to s33
2020-03-19 15:35:16 -04:00
MSP430
…
NVPTX
ARM: Fixup some tests using denormal-fp-math attribute
2020-03-10 14:02:06 -04:00
PowerPC
[AIX] discard the label in the csect of function description and use qualname for linkage
2020-03-26 15:46:52 -04:00
RISCV
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
SPARC
[Sparc] Fix incorrect operand for matching CMPri pattern
2020-03-02 11:36:32 +08:00
SystemZ
[SystemZ] Improve foldMemoryOperandImpl()
2020-03-25 16:21:08 +01:00
Thumb
[DAGCombine] Skip PostInc combine with later users
2020-03-23 08:39:53 +00:00
Thumb2
[ARM] Sink splats to vector float instructions
2020-03-26 09:02:18 +00:00
VE
[VE] Target-specific bit size for sjljehprepare
2020-03-10 17:51:16 +01:00
WebAssembly
[WebAssembly] Support swiftself and swifterror for WebAssembly target
2020-03-19 17:39:52 -07:00
WinCFGuard
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WinEH
…
X86
[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.
2020-03-26 14:10:20 -07:00
XCore
[XCore] Add instruction pattern for bitrev
2020-02-21 09:28:49 +08:00