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llvm-project/llvm/test/CodeGen
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Peilin Guo 4c4dbeeeea [DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR 
For ISD::EXTRACT_SUBVECTOR, its second operand must be a constant
multiple of the known-minimum vector length of the result type.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D107795
2021-08-25 19:33:39 +08:00
..
AArch64
[DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR
2021-08-25 19:33:39 +08:00
AMDGPU
[DAGCombine] Check the legality of the index of EXTRACT_SUBVECTOR
2021-08-25 19:33:39 +08:00
ARC
[ARC] Add codegen for the readcyclecounter intrinsic along with disassembly for associated instructions
2021-08-24 11:53:20 -07:00
ARM
Allow rematerialization of virtual reg uses
2021-08-24 11:09:02 -07:00
AVR
[AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors'
2021-08-05 10:37:36 +08:00
BPF
BPF: avoid NE/EQ loop exit condition
2021-08-04 16:54:16 -07:00
Generic
[VP] Add vector-predicated reduction intrinsics
2021-08-17 17:56:35 +01:00
Hexagon
[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs
2021-07-27 18:36:28 -05:00
Inputs
…
Lanai
[Lanai] fix lowering wide returns
2021-08-05 21:08:09 -07:00
M68k
[M68k][test] Migrate MC tests related to MOVEM instruciton
2021-08-24 13:09:53 -07:00
Mips
Allow rematerialization of virtual reg uses
2021-08-24 11:09:02 -07:00
MIR
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
MSP430
…
NVPTX
[NVPTX] Add NVPTX intrinsics for CUDA PTX 6.5 ldmatrix instructions
2021-08-06 16:13:35 -07:00
PowerPC
[NFC] Add tests for i128 fshl on a few targets.
2021-08-24 11:43:35 -07:00
RISCV
Allow rematerialization of virtual reg uses
2021-08-24 11:09:02 -07:00
SPARC
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
SystemZ
SystemZ: Tidy up a mir test
2021-08-10 13:56:54 -04:00
Thumb
Allow rematerialization of virtual reg uses
2021-08-24 11:09:02 -07:00
Thumb2
Allow rematerialization of virtual reg uses
2021-08-24 11:09:02 -07:00
VE
[LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.
2021-06-29 11:00:11 -07:00
WebAssembly
[WebAssembly] Use SSAUpdaterBulk in LowerEmscriptenSjLj
2021-08-24 18:23:51 -07:00
WinCFGuard
…
WinEH
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
X86
Revert "[asan] Implemented intrinsic for the custom calling convention similar used by HWASan for X86."
2021-08-24 13:21:20 -07:00
XCore
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00