b812b7a45e
Since the beginning, the offset of a frame index has been consistently interpreted backwards. It was treating it as an offset from the scratch wave offset register as a frame register. The correct interpretation is the offset from the SP on entry to the function, before the prolog. Frame index elimination then should select either SP or another register as an FP. Treat the scratch wave offset on kernel entry as the pre-incremented SP. Rely more heavily on the standard hasFP and frame pointer elimination logic, and clean up the private reservation code. This saves a copy in most callee functions. The kernel prolog emission code is still kind of a mess relying on checking the uses of physical registers, which I would prefer to eliminate. Currently selection directly emits MUBUF instructions, which require using a reference to some register. Use the register chosen for SP, and then ignore this later. This should probably be cleaned up to use pseudos that don't refer to any specific base register until frame index elimination. Add a workaround for shaders using large numbers of SGPRs. I'm not sure these cases were ever working correctly, since as far as I can tell the logic for figuring out which SGPR is the scratch wave offset doesn't match up with the shader input initialization in the shader programming guide. llvm-svn: 362661
78 lines
2.8 KiB
C++
78 lines
2.8 KiB
C++
//===--------------------- SIFrameLowering.h --------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#define LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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#include "AMDGPUFrameLowering.h"
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namespace llvm {
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class SIInstrInfo;
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class SIMachineFunctionInfo;
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class SIRegisterInfo;
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class GCNSubtarget;
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class SIFrameLowering final : public AMDGPUFrameLowering {
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public:
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SIFrameLowering(StackDirection D, unsigned StackAl, int LAO,
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unsigned TransAl = 1) :
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AMDGPUFrameLowering(D, StackAl, LAO, TransAl) {}
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~SIFrameLowering() override = default;
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void emitEntryFunctionPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const;
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void emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS = nullptr) const override;
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void processFunctionBeforeFrameFinalized(
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MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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private:
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void emitFlatScratchInit(const GCNSubtarget &ST,
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MachineFunction &MF,
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MachineBasicBlock &MBB) const;
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unsigned getReservedPrivateSegmentBufferReg(
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const GCNSubtarget &ST,
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const SIInstrInfo *TII,
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const SIRegisterInfo *TRI,
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SIMachineFunctionInfo *MFI,
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MachineFunction &MF) const;
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unsigned getReservedPrivateSegmentWaveByteOffsetReg(
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const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI,
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SIMachineFunctionInfo *MFI, MachineFunction &MF) const;
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// Emit scratch setup code for AMDPAL or Mesa, assuming ResourceRegUsed is set.
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void emitEntryFunctionScratchSetup(const GCNSubtarget &ST, MachineFunction &MF,
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MachineBasicBlock &MBB, SIMachineFunctionInfo *MFI,
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MachineBasicBlock::iterator I, unsigned PreloadedPrivateBufferReg,
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unsigned ScratchRsrcReg) const;
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public:
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bool hasFP(const MachineFunction &MF) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIFRAMELOWERING_H
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