4312c4afd4
We are duplicating predicates if several parts of the combined predicate list contain the same condition. Added code to deduplicate the list. We have AssemblerPredicates and AssemblerPredicate in the PredicateControl, but we never use AssemblerPredicates with an actual list, so this one is dropped. This addresses the first part of the llvm bug 43886: https://bugs.llvm.org/show_bug.cgi?id=43886 Differential Revision: https://reviews.llvm.org/D69815
838 lines
36 KiB
TableGen
838 lines
36 KiB
TableGen
//===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// MIMG-specific encoding families to distinguish between semantically
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// equivalent machine instructions with different encoding.
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//
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// - MIMGEncGfx6: encoding introduced with gfx6 (obsoleted for atomics in gfx8)
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// - MIMGEncGfx8: encoding introduced with gfx8 for atomics
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// - MIMGEncGfx10Default: gfx default (non-NSA) encoding
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// - MIMGEncGfx10NSA: gfx10 NSA encoding
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class MIMGEncoding;
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def MIMGEncGfx6 : MIMGEncoding;
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def MIMGEncGfx8 : MIMGEncoding;
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def MIMGEncGfx10Default : MIMGEncoding;
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def MIMGEncGfx10NSA : MIMGEncoding;
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def MIMGEncoding : GenericEnum {
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let FilterClass = "MIMGEncoding";
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}
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// Represent an ISA-level opcode, independent of the encoding and the
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// vdata/vaddr size.
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class MIMGBaseOpcode : PredicateControl {
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MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
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bit Store = 0;
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bit Atomic = 0;
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bit AtomicX2 = 0; // (f)cmpswap
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bit Sampler = 0;
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bit Gather4 = 0;
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bits<8> NumExtraArgs = 0;
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bit Gradients = 0;
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bit Coordinates = 1;
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bit LodOrClampOrMip = 0;
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bit HasD16 = 0;
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}
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def MIMGBaseOpcode : GenericEnum {
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let FilterClass = "MIMGBaseOpcode";
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}
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def MIMGBaseOpcodesTable : GenericTable {
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let FilterClass = "MIMGBaseOpcode";
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let CppTypeName = "MIMGBaseOpcodeInfo";
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let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", "Gather4",
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"NumExtraArgs", "Gradients", "Coordinates", "LodOrClampOrMip",
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"HasD16"];
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GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode;
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let PrimaryKey = ["BaseOpcode"];
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let PrimaryKeyName = "getMIMGBaseOpcodeInfo";
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}
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def MIMGDim : GenericEnum {
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let FilterClass = "AMDGPUDimProps";
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}
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def MIMGDimInfoTable : GenericTable {
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let FilterClass = "AMDGPUDimProps";
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let CppTypeName = "MIMGDimInfo";
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let Fields = ["Dim", "NumCoords", "NumGradients", "DA", "Encoding", "AsmSuffix"];
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GenericEnum TypeOf_Dim = MIMGDim;
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let PrimaryKey = ["Dim"];
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let PrimaryKeyName = "getMIMGDimInfo";
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}
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def getMIMGDimInfoByEncoding : SearchIndex {
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let Table = MIMGDimInfoTable;
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let Key = ["Encoding"];
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}
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def getMIMGDimInfoByAsmSuffix : SearchIndex {
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let Table = MIMGDimInfoTable;
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let Key = ["AsmSuffix"];
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}
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class mimg <bits<8> si_gfx10, bits<8> vi = si_gfx10> {
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field bits<8> SI_GFX10 = si_gfx10;
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field bits<8> VI = vi;
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}
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class MIMGLZMapping<MIMGBaseOpcode l, MIMGBaseOpcode lz> {
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MIMGBaseOpcode L = l;
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MIMGBaseOpcode LZ = lz;
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}
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def MIMGLZMappingTable : GenericTable {
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let FilterClass = "MIMGLZMapping";
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let CppTypeName = "MIMGLZMappingInfo";
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let Fields = ["L", "LZ"];
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GenericEnum TypeOf_L = MIMGBaseOpcode;
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GenericEnum TypeOf_LZ = MIMGBaseOpcode;
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let PrimaryKey = ["L"];
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let PrimaryKeyName = "getMIMGLZMappingInfo";
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}
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class MIMGMIPMapping<MIMGBaseOpcode mip, MIMGBaseOpcode nonmip> {
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MIMGBaseOpcode MIP = mip;
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MIMGBaseOpcode NONMIP = nonmip;
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}
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def MIMGMIPMappingTable : GenericTable {
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let FilterClass = "MIMGMIPMapping";
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let CppTypeName = "MIMGMIPMappingInfo";
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let Fields = ["MIP", "NONMIP"];
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GenericEnum TypeOf_MIP = MIMGBaseOpcode;
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GenericEnum TypeOf_NONMIP = MIMGBaseOpcode;
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let PrimaryKey = ["MIP"];
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let PrimaryKeyName = "getMIMGMIPMappingInfo";
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}
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class MIMG_Base <dag outs, string dns = "">
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: InstSI <outs, (ins), "", []> {
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let VM_CNT = 1;
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let EXP_CNT = 1;
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let MIMG = 1;
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let Uses = [EXEC];
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let mayLoad = 1;
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let mayStore = 0;
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let SchedRW = [WriteVMEM];
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let UseNamedOperandTable = 1;
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let hasSideEffects = 0; // XXX ????
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let DecoderNamespace = dns;
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let isAsmParserOnly = !if(!eq(dns,""), 1, 0);
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let usesCustomInserter = 1;
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}
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class MIMG <dag outs, string dns = "">
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: MIMG_Base <outs, dns> {
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let hasPostISelHook = 1;
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let AsmMatchConverter = "cvtMIMG";
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Instruction Opcode = !cast<Instruction>(NAME);
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MIMGBaseOpcode BaseOpcode;
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MIMGEncoding MIMGEncoding;
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bits<8> VDataDwords;
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bits<8> VAddrDwords;
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}
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def MIMGInfoTable : GenericTable {
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let FilterClass = "MIMG";
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let CppTypeName = "MIMGInfo";
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let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
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GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode;
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GenericEnum TypeOf_MIMGEncoding = MIMGEncoding;
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let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
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let PrimaryKeyName = "getMIMGOpcodeHelper";
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}
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def getMIMGInfo : SearchIndex {
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let Table = MIMGInfoTable;
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let Key = ["Opcode"];
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}
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// This is a separate class so that TableGen memoizes the computations.
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class MIMGNSAHelper<int num_addrs> {
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list<string> AddrAsmNames =
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!foldl([]<string>, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11], lhs, i,
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!if(!lt(i, num_addrs), !listconcat(lhs, ["vaddr"#!size(lhs)]), lhs));
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dag AddrIns = !dag(ins, !foreach(arg, AddrAsmNames, VGPR_32), AddrAsmNames);
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string AddrAsm = "[" # !foldl("$" # !head(AddrAsmNames), !tail(AddrAsmNames), lhs, rhs,
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lhs # ", $" # rhs) # "]";
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int NSA = !if(!le(num_addrs, 1), ?,
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!if(!le(num_addrs, 5), 1,
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!if(!le(num_addrs, 9), 2,
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!if(!le(num_addrs, 13), 3, ?))));
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}
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// Base class of all pre-gfx10 MIMG instructions.
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class MIMG_gfx6789<bits<8> op, dag outs, string dns = "">
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: MIMG<outs, dns>, MIMGe_gfx6789<op> {
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let SubtargetPredicate = isGFX6GFX7GFX8GFX9;
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let AssemblerPredicate = isGFX6GFX7GFX8GFX9;
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let MIMGEncoding = MIMGEncGfx6;
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let d16 = !if(BaseOpcode.HasD16, ?, 0);
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}
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// Base class of all non-NSA gfx10 MIMG instructions.
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class MIMG_gfx10<int op, dag outs, string dns = "">
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: MIMG<outs, dns>, MIMGe_gfx10<op> {
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let SubtargetPredicate = isGFX10Plus;
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let AssemblerPredicate = isGFX10Plus;
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let MIMGEncoding = MIMGEncGfx10Default;
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let d16 = !if(BaseOpcode.HasD16, ?, 0);
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let nsa = 0;
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}
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// Base class for all NSA MIMG instructions. Note that 1-dword addresses always
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// use non-NSA variants.
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class MIMG_nsa_gfx10<int op, dag outs, int num_addrs, string dns="">
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: MIMG<outs, dns>, MIMGe_gfx10<op> {
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let SubtargetPredicate = isGFX10Plus;
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let AssemblerPredicate = isGFX10Plus;
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let MIMGEncoding = MIMGEncGfx10NSA;
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MIMGNSAHelper nsah = MIMGNSAHelper<num_addrs>;
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dag AddrIns = nsah.AddrIns;
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string AddrAsm = nsah.AddrAsm;
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let d16 = !if(BaseOpcode.HasD16, ?, 0);
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let nsa = nsah.NSA;
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}
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class MIMG_NoSampler_Helper <bits<8> op, string asm,
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RegisterClass dst_rc,
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RegisterClass addr_rc,
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string dns="">
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: MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> {
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let InOperandList = !con((ins addr_rc:$vaddr, SReg_256:$srsrc,
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DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
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R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_NoSampler_gfx10<int op, string opcode,
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RegisterClass DataRC, RegisterClass AddrRC,
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string dns="">
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: MIMG_gfx10<op, (outs DataRC:$vdata), dns> {
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let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, DMask:$dmask,
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Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
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SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_NoSampler_nsa_gfx10<int op, string opcode,
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RegisterClass DataRC, int num_addrs,
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string dns="">
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: MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> {
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let InOperandList = !con(AddrIns,
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(ins SReg_256:$srsrc, DMask:$dmask,
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Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
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SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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multiclass MIMG_NoSampler_Src_Helper <bits<8> op, string asm,
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RegisterClass dst_rc,
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bit enableDisasm> {
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let ssamp = 0 in {
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let VAddrDwords = 1 in {
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def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
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!if(enableDisasm, "AMDGPU", "")>;
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def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
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!if(enableDisasm, "AMDGPU", "")>;
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}
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let VAddrDwords = 2 in {
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def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>;
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def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>;
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def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>;
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}
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let VAddrDwords = 3 in {
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def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>;
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def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>;
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def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>;
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}
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let VAddrDwords = 4 in {
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def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>;
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def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
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def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
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!if(enableDisasm, "AMDGPU", "")>;
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}
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}
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}
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multiclass MIMG_NoSampler <bits<8> op, string asm, bit has_d16, bit mip = 0,
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bit isResInfo = 0> {
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def "" : MIMGBaseOpcode {
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let Coordinates = !if(isResInfo, 0, 1);
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let LodOrClampOrMip = mip;
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let HasD16 = has_d16;
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}
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let BaseOpcode = !cast<MIMGBaseOpcode>(NAME),
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mayLoad = !if(isResInfo, 0, 1) in {
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let VDataDwords = 1 in
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defm _V1 : MIMG_NoSampler_Src_Helper <op, asm, VGPR_32, 1>;
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let VDataDwords = 2 in
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defm _V2 : MIMG_NoSampler_Src_Helper <op, asm, VReg_64, 0>;
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let VDataDwords = 3 in
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defm _V3 : MIMG_NoSampler_Src_Helper <op, asm, VReg_96, 0>;
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let VDataDwords = 4 in
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defm _V4 : MIMG_NoSampler_Src_Helper <op, asm, VReg_128, 0>;
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let VDataDwords = 5 in
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defm _V5 : MIMG_NoSampler_Src_Helper <op, asm, VReg_160, 0>;
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}
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}
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class MIMG_Store_Helper <bits<8> op, string asm,
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RegisterClass data_rc,
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RegisterClass addr_rc,
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string dns = "">
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: MIMG_gfx6789<op, (outs), dns> {
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let InOperandList = !con((ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
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DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
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R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = asm#" $vdata, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_Store_gfx10<int op, string opcode,
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RegisterClass DataRC, RegisterClass AddrRC,
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string dns="">
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: MIMG_gfx10<op, (outs), dns> {
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let InOperandList = !con((ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
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DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
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GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = opcode#" $vdata, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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class MIMG_Store_nsa_gfx10<int op, string opcode,
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RegisterClass DataRC, int num_addrs,
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string dns="">
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: MIMG_nsa_gfx10<op, (outs), num_addrs, dns> {
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let InOperandList = !con((ins DataRC:$vdata),
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AddrIns,
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(ins SReg_256:$srsrc, DMask:$dmask,
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Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
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SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
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!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe"
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#!if(BaseOpcode.HasD16, "$d16", "");
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}
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multiclass MIMG_Store_Addr_Helper <int op, string asm,
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RegisterClass data_rc,
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bit enableDisasm> {
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let mayLoad = 0, mayStore = 1, hasSideEffects = 0, hasPostISelHook = 0,
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DisableWQM = 1, ssamp = 0 in {
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let VAddrDwords = 1 in {
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def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
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!if(enableDisasm, "AMDGPU", "")>;
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def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32,
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!if(enableDisasm, "AMDGPU", "")>;
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}
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let VAddrDwords = 2 in {
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def _V2 : MIMG_Store_Helper <op, asm, data_rc, VReg_64>;
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def _V2_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_64>;
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def _V2_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 2>;
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}
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let VAddrDwords = 3 in {
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def _V3 : MIMG_Store_Helper <op, asm, data_rc, VReg_96>;
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def _V3_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_96>;
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def _V3_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 3>;
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}
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let VAddrDwords = 4 in {
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def _V4 : MIMG_Store_Helper <op, asm, data_rc, VReg_128>;
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def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>;
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def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4,
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!if(enableDisasm, "AMDGPU", "")>;
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}
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}
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}
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multiclass MIMG_Store <bits<8> op, string asm, bit has_d16, bit mip = 0> {
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def "" : MIMGBaseOpcode {
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let Store = 1;
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let LodOrClampOrMip = mip;
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let HasD16 = has_d16;
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}
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let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
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let VDataDwords = 1 in
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defm _V1 : MIMG_Store_Addr_Helper <op, asm, VGPR_32, 1>;
|
|
let VDataDwords = 2 in
|
|
defm _V2 : MIMG_Store_Addr_Helper <op, asm, VReg_64, 0>;
|
|
let VDataDwords = 3 in
|
|
defm _V3 : MIMG_Store_Addr_Helper <op, asm, VReg_96, 0>;
|
|
let VDataDwords = 4 in
|
|
defm _V4 : MIMG_Store_Addr_Helper <op, asm, VReg_128, 0>;
|
|
}
|
|
}
|
|
|
|
class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, string dns="">
|
|
: MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
|
|
let Constraints = "$vdst = $vdata";
|
|
let AsmMatchConverter = "cvtMIMGAtomic";
|
|
|
|
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
|
|
DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
|
|
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
|
|
let AsmString = asm#" $vdst, $vaddr, $srsrc$dmask$unorm$glc$slc$r128$tfe$lwe$da";
|
|
}
|
|
|
|
class MIMG_Atomic_si<mimg op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, bit enableDasm = 0>
|
|
: MIMG_Atomic_gfx6789_base<op.SI_GFX10, asm, data_rc, addr_rc,
|
|
!if(enableDasm, "GFX6GFX7", "")> {
|
|
let AssemblerPredicate = isGFX6GFX7;
|
|
}
|
|
|
|
class MIMG_Atomic_vi<mimg op, string asm, RegisterClass data_rc,
|
|
RegisterClass addr_rc, bit enableDasm = 0>
|
|
: MIMG_Atomic_gfx6789_base<op.VI, asm, data_rc, addr_rc, !if(enableDasm, "GFX8", "")> {
|
|
let AssemblerPredicate = isGFX8GFX9;
|
|
let MIMGEncoding = MIMGEncGfx8;
|
|
}
|
|
|
|
class MIMG_Atomic_gfx10<mimg op, string opcode,
|
|
RegisterClass DataRC, RegisterClass AddrRC,
|
|
bit enableDisasm = 0>
|
|
: MIMG_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst),
|
|
!if(enableDisasm, "AMDGPU", "")> {
|
|
let Constraints = "$vdst = $vdata";
|
|
let AsmMatchConverter = "cvtMIMGAtomic";
|
|
|
|
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
|
|
DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
|
|
GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe);
|
|
let AsmString = opcode#" $vdst, $vaddr0, $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe";
|
|
}
|
|
|
|
class MIMG_Atomic_nsa_gfx10<mimg op, string opcode,
|
|
RegisterClass DataRC, int num_addrs,
|
|
bit enableDisasm = 0>
|
|
: MIMG_nsa_gfx10<!cast<int>(op.SI_GFX10), (outs DataRC:$vdst), num_addrs,
|
|
!if(enableDisasm, "AMDGPU", "")> {
|
|
let Constraints = "$vdst = $vdata";
|
|
let AsmMatchConverter = "cvtMIMGAtomic";
|
|
|
|
let InOperandList = !con((ins DataRC:$vdata),
|
|
AddrIns,
|
|
(ins SReg_256:$srsrc, DMask:$dmask,
|
|
Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
|
|
SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe));
|
|
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc$dmask$dim$unorm$dlc$glc$slc$r128$tfe$lwe";
|
|
}
|
|
|
|
multiclass MIMG_Atomic_Addr_Helper_m <mimg op, string asm,
|
|
RegisterClass data_rc,
|
|
bit enableDasm = 0> {
|
|
let hasSideEffects = 1, // FIXME: remove this
|
|
mayLoad = 1, mayStore = 1, hasPostISelHook = 0, DisableWQM = 1,
|
|
ssamp = 0 in {
|
|
let VAddrDwords = 1 in {
|
|
def _V1_si : MIMG_Atomic_si <op, asm, data_rc, VGPR_32, enableDasm>;
|
|
def _V1_vi : MIMG_Atomic_vi <op, asm, data_rc, VGPR_32, enableDasm>;
|
|
def _V1_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VGPR_32, enableDasm>;
|
|
}
|
|
let VAddrDwords = 2 in {
|
|
def _V2_si : MIMG_Atomic_si <op, asm, data_rc, VReg_64, 0>;
|
|
def _V2_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_64, 0>;
|
|
def _V2_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_64, 0>;
|
|
def _V2_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 2, 0>;
|
|
}
|
|
let VAddrDwords = 3 in {
|
|
def _V3_si : MIMG_Atomic_si <op, asm, data_rc, VReg_96, 0>;
|
|
def _V3_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_96, 0>;
|
|
def _V3_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_96, 0>;
|
|
def _V3_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 3, 0>;
|
|
}
|
|
let VAddrDwords = 4 in {
|
|
def _V4_si : MIMG_Atomic_si <op, asm, data_rc, VReg_128, 0>;
|
|
def _V4_vi : MIMG_Atomic_vi <op, asm, data_rc, VReg_128, 0>;
|
|
def _V4_gfx10 : MIMG_Atomic_gfx10 <op, asm, data_rc, VReg_128, 0>;
|
|
def _V4_nsa_gfx10 : MIMG_Atomic_nsa_gfx10 <op, asm, data_rc, 4, enableDasm>;
|
|
}
|
|
}
|
|
}
|
|
|
|
multiclass MIMG_Atomic <mimg op, string asm, bit isCmpSwap = 0> { // 64-bit atomics
|
|
def "" : MIMGBaseOpcode {
|
|
let Atomic = 1;
|
|
let AtomicX2 = isCmpSwap;
|
|
}
|
|
|
|
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME) in {
|
|
// _V* variants have different dst size, but the size is encoded implicitly,
|
|
// using dmask and tfe. Only 32-bit variant is registered with disassembler.
|
|
// Other variants are reconstructed by disassembler using dmask and tfe.
|
|
let VDataDwords = !if(isCmpSwap, 2, 1) in
|
|
defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1>;
|
|
let VDataDwords = !if(isCmpSwap, 4, 2) in
|
|
defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64)>;
|
|
}
|
|
}
|
|
|
|
class MIMG_Sampler_Helper <bits<8> op, string asm, RegisterClass dst_rc,
|
|
RegisterClass src_rc, string dns="">
|
|
: MIMG_gfx6789 <op, (outs dst_rc:$vdata), dns> {
|
|
let InOperandList = !con((ins src_rc:$vaddr, SReg_256:$srsrc, SReg_128:$ssamp,
|
|
DMask:$dmask, UNorm:$unorm, GLC:$glc, SLC:$slc,
|
|
R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = asm#" $vdata, $vaddr, $srsrc, $ssamp$dmask$unorm$glc$slc$r128$tfe$lwe$da"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMG_Sampler_gfx10<int op, string opcode,
|
|
RegisterClass DataRC, RegisterClass AddrRC,
|
|
string dns="">
|
|
: MIMG_gfx10<op, (outs DataRC:$vdata), dns> {
|
|
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256:$srsrc, SReg_128:$ssamp,
|
|
DMask:$dmask, Dim:$dim, UNorm:$unorm, DLC:$dlc,
|
|
GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = opcode#" $vdata, $vaddr0, $srsrc, $ssamp$dmask$dim$unorm"
|
|
#"$dlc$glc$slc$r128$tfe$lwe"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMG_Sampler_nsa_gfx10<int op, string opcode,
|
|
RegisterClass DataRC, int num_addrs,
|
|
string dns="">
|
|
: MIMG_nsa_gfx10<op, (outs DataRC:$vdata), num_addrs, dns> {
|
|
let InOperandList = !con(AddrIns,
|
|
(ins SReg_256:$srsrc, SReg_128:$ssamp, DMask:$dmask,
|
|
Dim:$dim, UNorm:$unorm, DLC:$dlc, GLC:$glc,
|
|
SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
|
|
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
|
|
let AsmString = opcode#" $vdata, "#AddrAsm#", $srsrc, $ssamp$dmask$dim$unorm"
|
|
#"$dlc$glc$slc$r128$tfe$lwe"
|
|
#!if(BaseOpcode.HasD16, "$d16", "");
|
|
}
|
|
|
|
class MIMGAddrSize<int dw, bit enable_disasm> {
|
|
int NumWords = dw;
|
|
|
|
RegisterClass RegClass = !if(!le(NumWords, 0), ?,
|
|
!if(!eq(NumWords, 1), VGPR_32,
|
|
!if(!eq(NumWords, 2), VReg_64,
|
|
!if(!eq(NumWords, 3), VReg_96,
|
|
!if(!eq(NumWords, 4), VReg_128,
|
|
!if(!le(NumWords, 8), VReg_256,
|
|
!if(!le(NumWords, 16), VReg_512, ?)))))));
|
|
|
|
// Whether the instruction variant with this vaddr size should be enabled for
|
|
// the auto-generated disassembler.
|
|
bit Disassemble = enable_disasm;
|
|
}
|
|
|
|
// Return whether x is in lst.
|
|
class isIntInList<int x, list<int> lst> {
|
|
bit ret = !foldl(0, lst, lhs, y, !or(lhs, !eq(x, y)));
|
|
}
|
|
|
|
// Return whether a value inside the range [min, max] (endpoints inclusive)
|
|
// is in the given list.
|
|
class isRangeInList<int min, int max, list<int> lst> {
|
|
bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max))));
|
|
}
|
|
|
|
class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> {
|
|
list<MIMGAddrSize> List = lst;
|
|
int Min = min;
|
|
}
|
|
|
|
class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
|
|
// List of all possible numbers of address words, taking all combinations of
|
|
// A16 and image dimension into account (note: no MSAA, since this is for
|
|
// sample/gather ops).
|
|
list<int> AllNumAddrWords =
|
|
!foreach(dw, !if(sample.Gradients,
|
|
!if(!eq(sample.LodOrClamp, ""),
|
|
[2, 3, 4, 5, 6, 7, 9],
|
|
[2, 3, 4, 5, 7, 8, 10]),
|
|
!if(!eq(sample.LodOrClamp, ""),
|
|
[1, 2, 3],
|
|
[1, 2, 3, 4])),
|
|
!add(dw, !size(sample.ExtraAddrArgs)));
|
|
|
|
// Generate machine instructions based on possible register classes for the
|
|
// required numbers of address words. The disassembler defaults to the
|
|
// smallest register class.
|
|
list<MIMGAddrSize> MachineInstrs =
|
|
!foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 8, 16], lhs, dw,
|
|
!if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret,
|
|
MIMGAddrSizes_tmp<
|
|
!listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]),
|
|
!if(!eq(dw, 3), 3, !add(dw, 1))>, // we still need _V4 for codegen w/ 3 dwords
|
|
lhs)).List;
|
|
|
|
// For NSA, generate machine instructions for all possible numbers of words
|
|
// except 1 (which is already covered by the non-NSA case).
|
|
// The disassembler defaults to the largest number of arguments among the
|
|
// variants with the same number of NSA words, and custom code then derives
|
|
// the exact variant based on the sample variant and the image dimension.
|
|
list<MIMGAddrSize> NSAInstrs =
|
|
!foldl([]<MIMGAddrSize>, [[12, 11, 10], [9, 8, 7, 6], [5, 4, 3, 2]], prev, nsa_group,
|
|
!listconcat(prev,
|
|
!foldl([]<MIMGAddrSize>, nsa_group, lhs, dw,
|
|
!if(isIntInList<dw, AllNumAddrWords>.ret,
|
|
!listconcat(lhs, [MIMGAddrSize<dw, !empty(lhs)>]),
|
|
lhs))));
|
|
}
|
|
|
|
multiclass MIMG_Sampler_Src_Helper <bits<8> op, string asm,
|
|
AMDGPUSampleVariant sample, RegisterClass dst_rc,
|
|
bit enableDisasm = 0> {
|
|
foreach addr = MIMG_Sampler_AddrSizes<sample>.MachineInstrs in {
|
|
let VAddrDwords = addr.NumWords in {
|
|
def _V # addr.NumWords
|
|
: MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
|
|
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
|
|
def _V # addr.NumWords # _gfx10
|
|
: MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass,
|
|
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
|
|
}
|
|
}
|
|
|
|
foreach addr = MIMG_Sampler_AddrSizes<sample>.NSAInstrs in {
|
|
let VAddrDwords = addr.NumWords in {
|
|
def _V # addr.NumWords # _nsa_gfx10
|
|
: MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords,
|
|
!if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
|
|
}
|
|
}
|
|
}
|
|
|
|
class MIMG_Sampler_BaseOpcode<AMDGPUSampleVariant sample>
|
|
: MIMGBaseOpcode {
|
|
let Sampler = 1;
|
|
let NumExtraArgs = !size(sample.ExtraAddrArgs);
|
|
let Gradients = sample.Gradients;
|
|
let LodOrClampOrMip = !ne(sample.LodOrClamp, "");
|
|
}
|
|
|
|
multiclass MIMG_Sampler <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
|
|
bit isGetLod = 0,
|
|
string asm = "image_sample"#sample.LowerCaseMod> {
|
|
def "" : MIMG_Sampler_BaseOpcode<sample> {
|
|
let HasD16 = !if(isGetLod, 0, 1);
|
|
}
|
|
|
|
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
|
|
mayLoad = !if(isGetLod, 0, 1) in {
|
|
let VDataDwords = 1 in
|
|
defm _V1 : MIMG_Sampler_Src_Helper<op, asm, sample, VGPR_32, 1>;
|
|
let VDataDwords = 2 in
|
|
defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>;
|
|
let VDataDwords = 3 in
|
|
defm _V3 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_96>;
|
|
let VDataDwords = 4 in
|
|
defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128>;
|
|
let VDataDwords = 5 in
|
|
defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>;
|
|
}
|
|
}
|
|
|
|
multiclass MIMG_Sampler_WQM <bits<8> op, AMDGPUSampleVariant sample>
|
|
: MIMG_Sampler<op, sample, 1>;
|
|
|
|
multiclass MIMG_Gather <bits<8> op, AMDGPUSampleVariant sample, bit wqm = 0,
|
|
string asm = "image_gather4"#sample.LowerCaseMod> {
|
|
def "" : MIMG_Sampler_BaseOpcode<sample> {
|
|
let HasD16 = 1;
|
|
let Gather4 = 1;
|
|
}
|
|
|
|
let BaseOpcode = !cast<MIMGBaseOpcode>(NAME), WQM = wqm,
|
|
Gather4 = 1, hasPostISelHook = 0 in {
|
|
let VDataDwords = 2 in
|
|
defm _V2 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_64>; /* for packed D16 only */
|
|
let VDataDwords = 4 in
|
|
defm _V4 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_128, 1>;
|
|
let VDataDwords = 5 in
|
|
defm _V5 : MIMG_Sampler_Src_Helper<op, asm, sample, VReg_160>;
|
|
}
|
|
}
|
|
|
|
multiclass MIMG_Gather_WQM <bits<8> op, AMDGPUSampleVariant sample>
|
|
: MIMG_Gather<op, sample, 1>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// MIMG Instructions
|
|
//===----------------------------------------------------------------------===//
|
|
defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load", 1>;
|
|
defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip", 1, 1>;
|
|
defm IMAGE_LOAD_PCK : MIMG_NoSampler <0x00000002, "image_load_pck", 0>;
|
|
defm IMAGE_LOAD_PCK_SGN : MIMG_NoSampler <0x00000003, "image_load_pck_sgn", 0>;
|
|
defm IMAGE_LOAD_MIP_PCK : MIMG_NoSampler <0x00000004, "image_load_mip_pck", 0, 1>;
|
|
defm IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoSampler <0x00000005, "image_load_mip_pck_sgn", 0, 1>;
|
|
defm IMAGE_STORE : MIMG_Store <0x00000008, "image_store", 1>;
|
|
defm IMAGE_STORE_MIP : MIMG_Store <0x00000009, "image_store_mip", 1, 1>;
|
|
defm IMAGE_STORE_PCK : MIMG_Store <0x0000000a, "image_store_pck", 0>;
|
|
defm IMAGE_STORE_MIP_PCK : MIMG_Store <0x0000000b, "image_store_mip_pck", 0, 1>;
|
|
|
|
defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo", 0, 1, 1>;
|
|
|
|
defm IMAGE_ATOMIC_SWAP : MIMG_Atomic <mimg<0x0f, 0x10>, "image_atomic_swap">;
|
|
defm IMAGE_ATOMIC_CMPSWAP : MIMG_Atomic <mimg<0x10, 0x11>, "image_atomic_cmpswap", 1>;
|
|
defm IMAGE_ATOMIC_ADD : MIMG_Atomic <mimg<0x11, 0x12>, "image_atomic_add">;
|
|
defm IMAGE_ATOMIC_SUB : MIMG_Atomic <mimg<0x12, 0x13>, "image_atomic_sub">;
|
|
//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; -- not on VI
|
|
defm IMAGE_ATOMIC_SMIN : MIMG_Atomic <mimg<0x14>, "image_atomic_smin">;
|
|
defm IMAGE_ATOMIC_UMIN : MIMG_Atomic <mimg<0x15>, "image_atomic_umin">;
|
|
defm IMAGE_ATOMIC_SMAX : MIMG_Atomic <mimg<0x16>, "image_atomic_smax">;
|
|
defm IMAGE_ATOMIC_UMAX : MIMG_Atomic <mimg<0x17>, "image_atomic_umax">;
|
|
defm IMAGE_ATOMIC_AND : MIMG_Atomic <mimg<0x18>, "image_atomic_and">;
|
|
defm IMAGE_ATOMIC_OR : MIMG_Atomic <mimg<0x19>, "image_atomic_or">;
|
|
defm IMAGE_ATOMIC_XOR : MIMG_Atomic <mimg<0x1a>, "image_atomic_xor">;
|
|
defm IMAGE_ATOMIC_INC : MIMG_Atomic <mimg<0x1b>, "image_atomic_inc">;
|
|
defm IMAGE_ATOMIC_DEC : MIMG_Atomic <mimg<0x1c>, "image_atomic_dec">;
|
|
//let FPAtomic = 1 in {
|
|
//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d, 1>; -- not on VI
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//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; -- not on VI
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//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; -- not on VI
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//} // End let FPAtomic = 1
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defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, AMDGPUSample>;
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defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, AMDGPUSample_cl>;
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defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, AMDGPUSample_d>;
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defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, AMDGPUSample_d_cl>;
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defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, AMDGPUSample_l>;
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defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, AMDGPUSample_b>;
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defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, AMDGPUSample_b_cl>;
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defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, AMDGPUSample_lz>;
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defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, AMDGPUSample_c>;
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defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, AMDGPUSample_c_cl>;
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defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, AMDGPUSample_c_d>;
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defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, AMDGPUSample_c_d_cl>;
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defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, AMDGPUSample_c_l>;
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defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, AMDGPUSample_c_b>;
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defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, AMDGPUSample_c_b_cl>;
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defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, AMDGPUSample_c_lz>;
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defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, AMDGPUSample_o>;
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defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, AMDGPUSample_cl_o>;
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defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, AMDGPUSample_d_o>;
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defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, AMDGPUSample_d_cl_o>;
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defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, AMDGPUSample_l_o>;
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defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, AMDGPUSample_b_o>;
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defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, AMDGPUSample_b_cl_o>;
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defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, AMDGPUSample_lz_o>;
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defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, AMDGPUSample_c_o>;
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defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, AMDGPUSample_c_cl_o>;
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defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, AMDGPUSample_c_d_o>;
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defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, AMDGPUSample_c_d_cl_o>;
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defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, AMDGPUSample_c_l_o>;
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defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, AMDGPUSample_c_b_cl_o>;
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defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, AMDGPUSample_c_b_o>;
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defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, AMDGPUSample_c_lz_o>;
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defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, AMDGPUSample>;
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defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, AMDGPUSample_cl>;
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defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, AMDGPUSample_l>;
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defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, AMDGPUSample_b>;
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defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, AMDGPUSample_b_cl>;
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defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, AMDGPUSample_lz>;
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defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, AMDGPUSample_c>;
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defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, AMDGPUSample_c_cl>;
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defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, AMDGPUSample_c_l>;
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defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, AMDGPUSample_c_b>;
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defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, AMDGPUSample_c_b_cl>;
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defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, AMDGPUSample_c_lz>;
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defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, AMDGPUSample_o>;
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defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, AMDGPUSample_cl_o>;
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defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, AMDGPUSample_l_o>;
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defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, AMDGPUSample_b_o>;
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defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, AMDGPUSample_b_cl_o>;
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defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, AMDGPUSample_lz_o>;
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defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, AMDGPUSample_c_o>;
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defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, AMDGPUSample_c_cl_o>;
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defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, AMDGPUSample_c_l_o>;
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defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, AMDGPUSample_c_b_o>;
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defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, AMDGPUSample_c_b_cl_o>;
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defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, AMDGPUSample_c_lz_o>;
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defm IMAGE_GET_LOD : MIMG_Sampler <0x00000060, AMDGPUSample, 1, 1, "image_get_lod">;
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defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, AMDGPUSample_cd>;
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defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, AMDGPUSample_cd_cl>;
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defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, AMDGPUSample_c_cd>;
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defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, AMDGPUSample_c_cd_cl>;
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defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, AMDGPUSample_cd_o>;
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defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, AMDGPUSample_cd_cl_o>;
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defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, AMDGPUSample_c_cd_o>;
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defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, AMDGPUSample_c_cd_cl_o>;
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//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>;
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//def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>;
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/********** ========================================= **********/
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/********** Table of dimension-aware image intrinsics **********/
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/********** ========================================= **********/
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class ImageDimIntrinsicInfo<AMDGPUImageDimIntrinsic I> {
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Intrinsic Intr = I;
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MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(!strconcat("IMAGE_", I.P.OpMod));
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AMDGPUDimProps Dim = I.P.Dim;
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}
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def ImageDimIntrinsicTable : GenericTable {
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let FilterClass = "ImageDimIntrinsicInfo";
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let Fields = ["Intr", "BaseOpcode", "Dim"];
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GenericEnum TypeOf_BaseOpcode = MIMGBaseOpcode;
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GenericEnum TypeOf_Dim = MIMGDim;
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let PrimaryKey = ["Intr"];
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let PrimaryKeyName = "getImageDimIntrinsicInfo";
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let PrimaryKeyEarlyOut = 1;
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}
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foreach intr = !listconcat(AMDGPUImageDimIntrinsics,
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AMDGPUImageDimAtomicIntrinsics) in {
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def : ImageDimIntrinsicInfo<intr>;
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}
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// L to LZ Optimization Mapping
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def : MIMGLZMapping<IMAGE_SAMPLE_L, IMAGE_SAMPLE_LZ>;
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def : MIMGLZMapping<IMAGE_SAMPLE_C_L, IMAGE_SAMPLE_C_LZ>;
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def : MIMGLZMapping<IMAGE_SAMPLE_L_O, IMAGE_SAMPLE_LZ_O>;
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def : MIMGLZMapping<IMAGE_SAMPLE_C_L_O, IMAGE_SAMPLE_C_LZ_O>;
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def : MIMGLZMapping<IMAGE_GATHER4_L, IMAGE_GATHER4_LZ>;
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def : MIMGLZMapping<IMAGE_GATHER4_C_L, IMAGE_GATHER4_C_LZ>;
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def : MIMGLZMapping<IMAGE_GATHER4_L_O, IMAGE_GATHER4_LZ_O>;
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def : MIMGLZMapping<IMAGE_GATHER4_C_L_O, IMAGE_GATHER4_C_LZ_O>;
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// MIP to NONMIP Optimization Mapping
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def : MIMGMIPMapping<IMAGE_LOAD_MIP, IMAGE_LOAD>;
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def : MIMGMIPMapping<IMAGE_STORE_MIP, IMAGE_STORE>;
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