3a906a9f4e
Summary: Support for i<N> and fp32/64 arguments (in register), return values and constants along with tests. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D73092
60 lines
2.2 KiB
TableGen
60 lines
2.2 KiB
TableGen
//===-- VECallingConv.td - Calling Conventions VE ----------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the VE architectures.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Aurora VE
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//===----------------------------------------------------------------------===//
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def CC_VE : CallingConv<[
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// All arguments get passed in generic registers if there is space.
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// Promote i1/i8/i16 arguments to i32.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// bool, char, int, enum, long --> generic integer 32 bit registers
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CCIfType<[i32], CCAssignToRegWithShadow<
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[SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],
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[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
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// float --> generic floating point 32 bit registers
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CCIfType<[f32], CCAssignToRegWithShadow<
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[SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],
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[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
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// long long/double --> generic 64 bit registers
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CCIfType<[i64, f64],
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CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
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]>;
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def RetCC_VE : CallingConv<[
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// Promote i1/i8/i16 arguments to i32.
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CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
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// bool, char, int, enum, long --> generic integer 32 bit registers
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CCIfType<[i32], CCAssignToRegWithShadow<
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[SW0, SW1, SW2, SW3, SW4, SW5, SW6, SW7],
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[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
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// float --> generic floating point 32 bit registers
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CCIfType<[f32], CCAssignToRegWithShadow<
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[SF0, SF1, SF2, SF3, SF4, SF5, SF6, SF7],
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[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
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// long long/double --> generic 64 bit registers
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CCIfType<[i64, f64],
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CCAssignToReg<[SX0, SX1, SX2, SX3, SX4, SX5, SX6, SX7]>>,
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]>;
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// Callee-saved registers
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def CSR : CalleeSavedRegs<(add (sequence "SX%u", 18, 33))>;
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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