86acaa9457
Summary: This patch associates ordinal numbers to the DDG Nodes allowing the builder to order nodes within a pi-block in program order. The algorithm works by simply assuming the order in which the BBList is fed into the builder. The builder already relies on the blocks being in program order so that it can compute the dependencies correctly. Similarly the order of instructions in their parent basic blocks determine their program order. Authored By: bmahjour Reviewer: Meinersbur, fhahn, myhsu, xtian, dmgreen, kbarton, jdoerfert Reviewed By: Meinersbur Subscribers: ychen, arphaman, simoll, a.elovikov, mgorny, hiraditya, jfb, wuzish, llvm-commits, jsji, Whitney, etiotto, ppc-slack Tags: #llvm Differential Revision: https://reviews.llvm.org/D70986
202 lines
7.0 KiB
LLVM
202 lines
7.0 KiB
LLVM
; RUN: opt < %s -disable-output "-passes=print<ddg>" 2>&1 | FileCheck %s
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; CHECK-LABEL: 'DDG' for loop 'test1.for.body':
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; CHECK: Node Address:[[PI:0x[0-9a-f]*]]:pi-block
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; CHECK-NEXT: --- start of nodes in pi-block ---
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; CHECK: Node Address:[[N1:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %i.02 = phi i64 [ %inc, %test1.for.body ], [ 0, %test1.for.body.preheader ]
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N2:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N2]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %inc = add i64 %i.02, 1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N1]]
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; CHECK-NEXT: --- end of nodes in pi-block ---
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N3:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N4:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N5:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N5]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %exitcond = icmp ne i64 %inc, %n
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N6:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N6]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: br i1 %exitcond, label %test1.for.body, label %for.end.loopexit
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N4]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx1 = getelementptr inbounds float, float* %a, i64 %i.02
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N7:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N3]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx = getelementptr inbounds float, float* %b, i64 %i.02
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N8:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N8]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %0 = load float, float* %arrayidx, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N9:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N10:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %conv = uitofp i64 %n to float
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N9]]
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; CHECK: Node Address:[[N9]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %add = fadd float %0, %conv
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N7]]
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; CHECK: Node Address:[[N7]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: store float %add, float* %arrayidx1, align 4
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; CHECK-NEXT: Edges:none!
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;; No memory dependencies.
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;; void test1(unsigned long n, float * restrict a, float * restrict b) {
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;; for (unsigned long i = 0; i < n; i++)
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;; a[i] = b[i] + n;
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;; }
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define void @test1(i64 %n, float* noalias %a, float* noalias %b) {
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entry:
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%exitcond1 = icmp ne i64 0, %n
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br i1 %exitcond1, label %test1.for.body, label %for.end
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test1.for.body: ; preds = %entry, %test1.for.body
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%i.02 = phi i64 [ %inc, %test1.for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds float, float* %b, i64 %i.02
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%0 = load float, float* %arrayidx, align 4
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%conv = uitofp i64 %n to float
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%add = fadd float %0, %conv
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%arrayidx1 = getelementptr inbounds float, float* %a, i64 %i.02
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store float %add, float* %arrayidx1, align 4
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%inc = add i64 %i.02, 1
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%exitcond = icmp ne i64 %inc, %n
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br i1 %exitcond, label %test1.for.body, label %for.end
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for.end: ; preds = %test1.for.body, %entry
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ret void
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}
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; CHECK-LABEL: 'DDG' for loop 'test2.for.body':
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; CHECK: Node Address:[[PI:0x[0-9a-f]*]]:pi-block
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; CHECK-NEXT: --- start of nodes in pi-block ---
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; CHECK: Node Address:[[N1:0x[0-9a-f]*]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %i.02 = phi i64 [ %inc, %test2.for.body ], [ 0, %test2.for.body.preheader ]
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N2:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N2]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %inc = add i64 %i.02, 1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N1]]
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; CHECK-NEXT: --- end of nodes in pi-block ---
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N3:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N4:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N5:0x[0-9a-f]*]]
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; CHECK-NEXT: [def-use] to [[N6:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N6]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %exitcond = icmp ne i64 %inc, %n
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N7:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N7]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: br i1 %exitcond, label %test2.for.body, label %for.end.loopexit
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; CHECK-NEXT: Edges:none!
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; CHECK: Node Address:[[N5]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx2 = getelementptr inbounds float, float* %a, i64 %i.02
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N8:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N4]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx1 = getelementptr inbounds float, float* %a, i64 %i.02
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N9:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N9]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %1 = load float, float* %arrayidx1, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N20:0x[0-9a-f]*]]
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; CHECK-NEXT: [memory] to [[N8]]
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; CHECK: Node Address:[[N3]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %arrayidx = getelementptr inbounds float, float* %b, i64 %i.02
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N10:0x[0-9a-f]*]]
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; CHECK: Node Address:[[N10]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %0 = load float, float* %arrayidx, align 4
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N20]]
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; CHECK: Node Address:[[N20]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: %add = fadd float %0, %1
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; CHECK-NEXT: Edges:
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; CHECK-NEXT: [def-use] to [[N8]]
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; CHECK: Node Address:[[N8]]:single-instruction
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; CHECK-NEXT: Instructions:
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; CHECK-NEXT: store float %add, float* %arrayidx2, align 4
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; CHECK-NEXT: Edges:none!
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;; Loop-independent memory dependencies.
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;; void test2(unsigned long n, float * restrict a, float * restrict b) {
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;; for (unsigned long i = 0; i < n; i++)
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;; a[i] = b[i] + a[i];
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;; }
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define void @test2(i64 %n, float* noalias %a, float* noalias %b) {
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entry:
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%exitcond1 = icmp ne i64 0, %n
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br i1 %exitcond1, label %test2.for.body, label %for.end
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test2.for.body: ; preds = %entry, %test2.for.body
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%i.02 = phi i64 [ %inc, %test2.for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds float, float* %b, i64 %i.02
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%0 = load float, float* %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds float, float* %a, i64 %i.02
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%1 = load float, float* %arrayidx1, align 4
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%add = fadd float %0, %1
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%arrayidx2 = getelementptr inbounds float, float* %a, i64 %i.02
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store float %add, float* %arrayidx2, align 4
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%inc = add i64 %i.02, 1
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%exitcond = icmp ne i64 %inc, %n
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br i1 %exitcond, label %test2.for.body, label %for.end
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for.end: ; preds = %test2.for.body, %entry
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ret void
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} |