c4d256a590
Detailed description:
After https://reviews.llvm.org/D59990 submit several issues were discovered.
Changes in common code were preserved but AMDGPU specific part was reverted to keep the backend working correctly.
Discovered issues were addressed in the following commits:
https://reviews.llvm.org/D67662
https://reviews.llvm.org/D67101
https://reviews.llvm.org/D63953
https://reviews.llvm.org/D63731
This change brings back AMDGPU specific changes.
Reviewed by: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D68635
llvm-svn: 374767
68 lines
2.6 KiB
LLVM
68 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
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; SI-LABEL: main:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: v_cvt_i32_f32_e32 v0, v0
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; SI-NEXT: s_mov_b32 s0, 0
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; SI-NEXT: s_mov_b32 s1, s0
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; SI-NEXT: s_mov_b32 s2, s0
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; SI-NEXT: s_mov_b32 s3, s0
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s0
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; SI-NEXT: s_mov_b32 s6, s0
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; SI-NEXT: s_mov_b32 s7, s0
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; SI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
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; SI-NEXT: v_and_b32_e32 v0, 7, v0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshrrev_b32_e32 v0, v0, v2
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; SI-NEXT: v_and_b32_e32 v0, 1, v0
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; SI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; SI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v0, s0, v0
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; SI-NEXT: ; return to shader part epilog
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;
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; VI-LABEL: main:
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; VI: ; %bb.0: ; %bb
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; VI-NEXT: v_cvt_i32_f32_e32 v0, v0
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; VI-NEXT: s_mov_b32 s0, 0
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; VI-NEXT: s_mov_b32 s1, s0
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; VI-NEXT: s_mov_b32 s2, s0
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; VI-NEXT: s_mov_b32 s3, s0
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; VI-NEXT: s_mov_b32 s4, s0
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; VI-NEXT: s_mov_b32 s5, s0
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; VI-NEXT: s_mov_b32 s6, s0
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; VI-NEXT: s_mov_b32 s7, s0
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; VI-NEXT: image_load v2, v0, s[0:7] dmask:0x1 unorm
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; VI-NEXT: v_and_b32_e32 v0, 7, v0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshrrev_b32_e32 v0, v0, v2
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; VI-NEXT: v_and_b32_e32 v0, 1, v0
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; VI-NEXT: v_cmp_eq_u32_e32 vcc, 1, v0
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; VI-NEXT: v_cndmask_b32_e32 v0, 0, v1, vcc
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; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, s0, v0
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; VI-NEXT: ; return to shader part epilog
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bb:
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%tmp = fptosi float %arg0 to i32
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%tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)
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%tmp2.f = extractelement <4 x float> %tmp1, i32 0
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%tmp2 = bitcast float %tmp2.f to i32
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%tmp3 = and i32 %tmp, 7
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%tmp4 = shl i32 1, %tmp3
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%tmp5 = and i32 %tmp2, %tmp4
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%tmp6 = icmp eq i32 %tmp5, 0
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%tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1
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%tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7)
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%tmp9 = bitcast <2 x half> %tmp8 to float
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ret float %tmp9
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}
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declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind readonly }
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