f24ec7bdd0
When switched to the MI scheduler for P9, the hardware is modeled as out of order. However, inside the MI Scheduler algorithm, we still use the in-order scheduling model as the MicroOpBufferSize isn't set. The MI scheduler take it as the hw cannot buffer the op. So, only when all the available instructions issued, the pending instruction could be scheduled. That is not true for our P9 hw in fact. This patch is trying to enable the Out-of-Order scheduling model. The buffer size 44 is picked from the P9 hw spec, and the perf test indicate that, its value won't hurt the cpu2017. With this patch, there are 3 specs improved over 3% and 1 spec deg over 3%. The detail is as follows: x264_r: +6.95% cactuBSSN_r: +6.94% lbm_r: +4.11% xz_r: -3.85% And the GEOMEAN for all the C/C++ spec in spec2017 is about 0.18% improved. Reviewer: Nemanjai Differential Revision: https://reviews.llvm.org/D55810 llvm-svn: 350285
112 lines
3.9 KiB
LLVM
112 lines
3.9 KiB
LLVM
; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr8 -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -O3 < %s | FileCheck %s
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; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: < %s | FileCheck %s --check-prefix=CHECK-P9 \
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; RUN: --implicit-check-not xxswapd
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; RUN: llc -relocation-model=pic -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu -O3 \
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; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mattr=-power9-vector < %s | FileCheck %s --check-prefix=CHECK-P9-NOVECTOR
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; These tests verify that VSX swap optimization works when loading a scalar
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; into a vector register.
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@x = global <2 x double> <double 9.970000e+01, double -1.032220e+02>, align 16
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@z = global <2 x double> <double 2.332000e+01, double 3.111111e+01>, align 16
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@y = global double 1.780000e+00, align 8
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define void @bar0() {
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; CHECK-LABEL: bar0:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis r3, r2, .LC0@toc@ha
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; CHECK: addis r4, r2, .LC1@toc@ha
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; CHECK: ld r3, .LC0@toc@l(r3)
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; CHECK: addis r3, r2, .LC2@toc@ha
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; CHECK: ld r3, .LC2@toc@l(r3)
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; CHECK: xxpermdi vs0, vs0, vs1, 1
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; CHECK: stxvd2x vs0, 0, r3
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; CHECK: blr
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;
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; CHECK-P9-NOVECTOR-LABEL: bar0:
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; CHECK-P9-NOVECTOR: # %bb.0: # %entry
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NOVECTOR: xxpermdi vs0, vs1, vs0, 1
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; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR: blr
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;
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; CHECK-P9-LABEL: bar0:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9: addis r3, r2, .LC0@toc@ha
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; CHECK-P9: ld r3, .LC0@toc@l(r3)
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; CHECK-P9: lxvx vs0, 0, r3
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; CHECK-P9: addis r3, r2, .LC1@toc@ha
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; CHECK-P9: ld r3, .LC1@toc@l(r3)
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; CHECK-P9: lfd f1, 0(r3)
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; CHECK-P9: addis r3, r2, .LC2@toc@ha
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; CHECK-P9: ld r3, .LC2@toc@l(r3)
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; CHECK-P9: xxpermdi vs1, f1, f1, 2
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; CHECK-P9: xxpermdi vs0, vs0, vs1, 1
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; CHECK-P9: stxvx vs0, 0, r3
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; CHECK-P9: blr
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 0
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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define void @bar1() {
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; CHECK-LABEL: bar1:
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; CHECK: # %bb.0: # %entry
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; CHECK: addis r3, r2, .LC0@toc@ha
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; CHECK: addis r4, r2, .LC1@toc@ha
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; CHECK: ld r3, .LC0@toc@l(r3)
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; CHECK: addis r3, r2, .LC2@toc@ha
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; CHECK: ld r3, .LC2@toc@l(r3)
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; CHECK: xxmrghd vs0, vs1, vs0
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; CHECK: stxvd2x vs0, 0, r3
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; CHECK: blr
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;
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; CHECK-P9-NOVECTOR-LABEL: bar1:
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; CHECK-P9-NOVECTOR: # %bb.0: # %entry
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC0@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC0@toc@l(r3)
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC1@toc@ha
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; CHECK-P9-NOVECTOR: addis r3, r2, .LC2@toc@ha
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; CHECK-P9-NOVECTOR: ld r3, .LC2@toc@l(r3)
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; CHECK-P9-NOVECTOR: xxmrghd vs0, vs0, vs1
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; CHECK-P9-NOVECTOR: stxvd2x vs0, 0, r3
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; CHECK-P9-NOVECTOR: blr
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;
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; CHECK-P9-LABEL: bar1:
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; CHECK-P9: # %bb.0: # %entry
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; CHECK-P9: addis r3, r2, .LC0@toc@ha
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; CHECK-P9: ld r3, .LC0@toc@l(r3)
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; CHECK-P9: lxvx vs0, 0, r3
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; CHECK-P9: addis r3, r2, .LC1@toc@ha
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; CHECK-P9: ld r3, .LC1@toc@l(r3)
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; CHECK-P9: lfd f1, 0(r3)
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; CHECK-P9: addis r3, r2, .LC2@toc@ha
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; CHECK-P9: ld r3, .LC2@toc@l(r3)
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; CHECK-P9: xxpermdi vs1, f1, f1, 2
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; CHECK-P9: xxmrgld vs0, vs1, vs0
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; CHECK-P9: stxvx vs0, 0, r3
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; CHECK-P9: blr
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entry:
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%0 = load <2 x double>, <2 x double>* @x, align 16
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%1 = load double, double* @y, align 8
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%vecins = insertelement <2 x double> %0, double %1, i32 1
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store <2 x double> %vecins, <2 x double>* @z, align 16
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ret void
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}
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