228f88fdc8
This change implements support for the `cr` and `cf` register constraints (which allocate a RVC GPR or RVC FPR respectively), and the `N` modifier (which prints the raw encoding of a register rather than the name). The intention behind these additions is to make it easier to use inline assembly when assembling raw instructions that are not supported by the compiler, for instance when experimenting with new instructions or when supporting proprietary extensions outside the toolchain. These implement part of my proposal in riscv-non-isa/riscv-c-api-doc#92 As part of the implementation, I felt there was not enough coverage of inline assembly and the "in X" floating-point extensions, so I have added more regression tests around these configurations.
511 lines
18 KiB
C++
511 lines
18 KiB
C++
//===--- RISCV.cpp - Implement RISC-V target feature support --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements RISC-V TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "clang/Basic/Diagnostic.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#include <optional>
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using namespace clang;
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using namespace clang::targets;
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ArrayRef<const char *> RISCVTargetInfo::getGCCRegNames() const {
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// clang-format off
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static const char *const GCCRegNames[] = {
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// Integer registers
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"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
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"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
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"x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
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// Floating point registers
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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// Vector registers
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"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
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"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
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"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
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"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
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// CSRs
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"fflags", "frm", "vtype", "vl", "vxsat", "vxrm", "sf.vcix_state"
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};
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// clang-format on
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return llvm::ArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
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static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
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{{"zero"}, "x0"}, {{"ra"}, "x1"}, {{"sp"}, "x2"}, {{"gp"}, "x3"},
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{{"tp"}, "x4"}, {{"t0"}, "x5"}, {{"t1"}, "x6"}, {{"t2"}, "x7"},
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{{"s0"}, "x8"}, {{"s1"}, "x9"}, {{"a0"}, "x10"}, {{"a1"}, "x11"},
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{{"a2"}, "x12"}, {{"a3"}, "x13"}, {{"a4"}, "x14"}, {{"a5"}, "x15"},
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{{"a6"}, "x16"}, {{"a7"}, "x17"}, {{"s2"}, "x18"}, {{"s3"}, "x19"},
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{{"s4"}, "x20"}, {{"s5"}, "x21"}, {{"s6"}, "x22"}, {{"s7"}, "x23"},
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{{"s8"}, "x24"}, {{"s9"}, "x25"}, {{"s10"}, "x26"}, {{"s11"}, "x27"},
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{{"t3"}, "x28"}, {{"t4"}, "x29"}, {{"t5"}, "x30"}, {{"t6"}, "x31"},
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{{"ft0"}, "f0"}, {{"ft1"}, "f1"}, {{"ft2"}, "f2"}, {{"ft3"}, "f3"},
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{{"ft4"}, "f4"}, {{"ft5"}, "f5"}, {{"ft6"}, "f6"}, {{"ft7"}, "f7"},
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{{"fs0"}, "f8"}, {{"fs1"}, "f9"}, {{"fa0"}, "f10"}, {{"fa1"}, "f11"},
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{{"fa2"}, "f12"}, {{"fa3"}, "f13"}, {{"fa4"}, "f14"}, {{"fa5"}, "f15"},
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{{"fa6"}, "f16"}, {{"fa7"}, "f17"}, {{"fs2"}, "f18"}, {{"fs3"}, "f19"},
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{{"fs4"}, "f20"}, {{"fs5"}, "f21"}, {{"fs6"}, "f22"}, {{"fs7"}, "f23"},
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{{"fs8"}, "f24"}, {{"fs9"}, "f25"}, {{"fs10"}, "f26"}, {{"fs11"}, "f27"},
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{{"ft8"}, "f28"}, {{"ft9"}, "f29"}, {{"ft10"}, "f30"}, {{"ft11"}, "f31"}};
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return llvm::ArrayRef(GCCRegAliases);
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}
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bool RISCVTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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switch (*Name) {
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default:
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return false;
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case 'I':
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// A 12-bit signed immediate.
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Info.setRequiresImmediate(-2048, 2047);
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return true;
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case 'J':
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// Integer zero.
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Info.setRequiresImmediate(0);
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return true;
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case 'K':
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// A 5-bit unsigned immediate for CSR access instructions.
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Info.setRequiresImmediate(0, 31);
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return true;
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case 'f':
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// A floating-point register.
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Info.setAllowsRegister();
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return true;
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case 'A':
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// An address that is held in a general-purpose register.
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Info.setAllowsMemory();
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return true;
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case 's':
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case 'S': // A symbol or label reference with a constant offset
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Info.setAllowsRegister();
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return true;
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case 'c':
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// A RVC register - GPR or FPR
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if (Name[1] == 'r' || Name[1] == 'f') {
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Info.setAllowsRegister();
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Name += 1;
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return true;
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}
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return false;
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case 'v':
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// A vector register.
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if (Name[1] == 'r' || Name[1] == 'd' || Name[1] == 'm') {
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Info.setAllowsRegister();
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Name += 1;
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return true;
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}
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return false;
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}
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}
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std::string RISCVTargetInfo::convertConstraint(const char *&Constraint) const {
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std::string R;
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switch (*Constraint) {
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// c* and v* are two-letter constraints on RISC-V.
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case 'c':
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case 'v':
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R = std::string("^") + std::string(Constraint, 2);
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Constraint += 1;
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break;
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default:
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R = TargetInfo::convertConstraint(Constraint);
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break;
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}
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return R;
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}
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static unsigned getVersionValue(unsigned MajorVersion, unsigned MinorVersion) {
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return MajorVersion * 1000000 + MinorVersion * 1000;
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}
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void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__riscv");
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bool Is64Bit = getTriple().isRISCV64();
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Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
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StringRef CodeModel = getTargetOpts().CodeModel;
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unsigned FLen = ISAInfo->getFLen();
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unsigned MinVLen = ISAInfo->getMinVLen();
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unsigned MaxELen = ISAInfo->getMaxELen();
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unsigned MaxELenFp = ISAInfo->getMaxELenFp();
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if (CodeModel == "default")
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CodeModel = "small";
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if (CodeModel == "small")
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Builder.defineMacro("__riscv_cmodel_medlow");
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else if (CodeModel == "medium")
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Builder.defineMacro("__riscv_cmodel_medany");
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else if (CodeModel == "large")
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Builder.defineMacro("__riscv_cmodel_large");
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StringRef ABIName = getABI();
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if (ABIName == "ilp32f" || ABIName == "lp64f")
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Builder.defineMacro("__riscv_float_abi_single");
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else if (ABIName == "ilp32d" || ABIName == "lp64d")
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Builder.defineMacro("__riscv_float_abi_double");
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else
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Builder.defineMacro("__riscv_float_abi_soft");
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if (ABIName == "ilp32e" || ABIName == "lp64e")
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Builder.defineMacro("__riscv_abi_rve");
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Builder.defineMacro("__riscv_arch_test");
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for (auto &Extension : ISAInfo->getExtensions()) {
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auto ExtName = Extension.first;
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auto ExtInfo = Extension.second;
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Builder.defineMacro(Twine("__riscv_", ExtName),
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Twine(getVersionValue(ExtInfo.Major, ExtInfo.Minor)));
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}
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if (ISAInfo->hasExtension("zmmul"))
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Builder.defineMacro("__riscv_mul");
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if (ISAInfo->hasExtension("m")) {
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Builder.defineMacro("__riscv_div");
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Builder.defineMacro("__riscv_muldiv");
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}
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if (ISAInfo->hasExtension("a")) {
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Builder.defineMacro("__riscv_atomic");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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if (Is64Bit)
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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}
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if (FLen) {
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Builder.defineMacro("__riscv_flen", Twine(FLen));
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Builder.defineMacro("__riscv_fdiv");
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Builder.defineMacro("__riscv_fsqrt");
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}
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if (MinVLen) {
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Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen));
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Builder.defineMacro("__riscv_v_elen", Twine(MaxELen));
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Builder.defineMacro("__riscv_v_elen_fp", Twine(MaxELenFp));
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}
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if (ISAInfo->hasExtension("c"))
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Builder.defineMacro("__riscv_compressed");
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if (ISAInfo->hasExtension("zve32x")) {
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Builder.defineMacro("__riscv_vector");
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// Currently we support the v0.12 RISC-V V intrinsics.
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Builder.defineMacro("__riscv_v_intrinsic", Twine(getVersionValue(0, 12)));
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}
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auto VScale = getVScaleRange(Opts);
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if (VScale && VScale->first && VScale->first == VScale->second)
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Builder.defineMacro("__riscv_v_fixed_vlen",
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Twine(VScale->first * llvm::RISCV::RVVBitsPerBlock));
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if (FastScalarUnalignedAccess)
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Builder.defineMacro("__riscv_misaligned_fast");
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else
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Builder.defineMacro("__riscv_misaligned_avoid");
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if (ISAInfo->hasExtension("e")) {
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if (Is64Bit)
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Builder.defineMacro("__riscv_64e");
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else
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Builder.defineMacro("__riscv_32e");
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}
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}
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static constexpr Builtin::Info BuiltinInfo[] = {
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#include "clang/Basic/BuiltinsRISCVVector.def"
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#define BUILTIN(ID, TYPE, ATTRS) \
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{#ID, TYPE, ATTRS, nullptr, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \
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{#ID, TYPE, ATTRS, FEATURE, HeaderDesc::NO_HEADER, ALL_LANGUAGES},
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#include "clang/Basic/BuiltinsRISCV.inc"
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};
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ArrayRef<Builtin::Info> RISCVTargetInfo::getTargetBuiltins() const {
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return llvm::ArrayRef(BuiltinInfo,
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clang::RISCV::LastTSBuiltin - Builtin::FirstTSBuiltin);
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}
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bool RISCVTargetInfo::initFeatureMap(
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llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const {
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unsigned XLen = 32;
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if (getTriple().isRISCV64()) {
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Features["64bit"] = true;
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XLen = 64;
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} else {
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Features["32bit"] = true;
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}
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std::vector<std::string> AllFeatures = FeaturesVec;
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auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
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if (!ParseResult) {
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std::string Buffer;
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llvm::raw_string_ostream OutputErrMsg(Buffer);
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handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
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OutputErrMsg << ErrMsg.getMessage();
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});
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Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
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return false;
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}
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// Append all features, not just new ones, so we override any negatives.
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llvm::append_range(AllFeatures, (*ParseResult)->toFeatures());
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return TargetInfo::initFeatureMap(Features, Diags, CPU, AllFeatures);
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}
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std::optional<std::pair<unsigned, unsigned>>
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RISCVTargetInfo::getVScaleRange(const LangOptions &LangOpts) const {
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// RISCV::RVVBitsPerBlock is 64.
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unsigned VScaleMin = ISAInfo->getMinVLen() / llvm::RISCV::RVVBitsPerBlock;
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if (LangOpts.VScaleMin || LangOpts.VScaleMax) {
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// Treat Zvl*b as a lower bound on vscale.
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VScaleMin = std::max(VScaleMin, LangOpts.VScaleMin);
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unsigned VScaleMax = LangOpts.VScaleMax;
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if (VScaleMax != 0 && VScaleMax < VScaleMin)
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VScaleMax = VScaleMin;
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return std::pair<unsigned, unsigned>(VScaleMin ? VScaleMin : 1, VScaleMax);
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}
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if (VScaleMin > 0) {
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unsigned VScaleMax = ISAInfo->getMaxVLen() / llvm::RISCV::RVVBitsPerBlock;
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return std::make_pair(VScaleMin, VScaleMax);
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}
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return std::nullopt;
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}
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/// Return true if has this feature, need to sync with handleTargetFeatures.
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bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
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bool Is64Bit = getTriple().isRISCV64();
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auto Result = llvm::StringSwitch<std::optional<bool>>(Feature)
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.Case("riscv", true)
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.Case("riscv32", !Is64Bit)
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.Case("riscv64", Is64Bit)
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.Case("32bit", !Is64Bit)
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.Case("64bit", Is64Bit)
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.Case("experimental", HasExperimental)
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.Default(std::nullopt);
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if (Result)
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return *Result;
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return ISAInfo->hasExtension(Feature);
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}
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/// Perform initialization based on the user configured set of features.
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bool RISCVTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) {
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unsigned XLen = getTriple().isArch64Bit() ? 64 : 32;
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auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, Features);
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if (!ParseResult) {
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std::string Buffer;
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llvm::raw_string_ostream OutputErrMsg(Buffer);
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handleAllErrors(ParseResult.takeError(), [&](llvm::StringError &ErrMsg) {
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OutputErrMsg << ErrMsg.getMessage();
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});
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Diags.Report(diag::err_invalid_feature_combination) << OutputErrMsg.str();
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return false;
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} else {
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ISAInfo = std::move(*ParseResult);
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}
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if (ABI.empty())
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ABI = ISAInfo->computeDefaultABI().str();
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if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
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HasLegalHalfType = true;
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FastScalarUnalignedAccess =
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llvm::is_contained(Features, "+unaligned-scalar-mem");
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if (llvm::is_contained(Features, "+experimental"))
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HasExperimental = true;
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if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
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Diags.Report(diag::err_invalid_feature_combination)
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<< "ILP32E cannot be used with the D ISA extension";
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return false;
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}
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return true;
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}
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bool RISCVTargetInfo::isValidCPUName(StringRef Name) const {
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bool Is64Bit = getTriple().isArch64Bit();
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return llvm::RISCV::parseCPU(Name, Is64Bit);
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}
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void RISCVTargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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bool Is64Bit = getTriple().isArch64Bit();
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llvm::RISCV::fillValidCPUArchList(Values, Is64Bit);
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}
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bool RISCVTargetInfo::isValidTuneCPUName(StringRef Name) const {
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bool Is64Bit = getTriple().isArch64Bit();
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return llvm::RISCV::parseTuneCPU(Name, Is64Bit);
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}
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void RISCVTargetInfo::fillValidTuneCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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bool Is64Bit = getTriple().isArch64Bit();
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llvm::RISCV::fillValidTuneCPUArchList(Values, Is64Bit);
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}
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static void populateNegativeRISCVFeatures(std::vector<std::string> &Features) {
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auto RII = llvm::RISCVISAInfo::parseArchString(
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"rv64i", /* EnableExperimentalExtension */ true);
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if (llvm::errorToBool(RII.takeError()))
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llvm_unreachable("unsupport rv64i");
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std::vector<std::string> FeatStrings =
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(*RII)->toFeatures(/* AddAllExtensions */ true);
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Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
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}
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static void handleFullArchString(StringRef FullArchStr,
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std::vector<std::string> &Features) {
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auto RII = llvm::RISCVISAInfo::parseArchString(
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FullArchStr, /* EnableExperimentalExtension */ true);
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if (llvm::errorToBool(RII.takeError())) {
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// Forward the invalid FullArchStr.
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Features.push_back(FullArchStr.str());
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} else {
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// Append a full list of features, including any negative extensions so that
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// we override the CPU's features.
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populateNegativeRISCVFeatures(Features);
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std::vector<std::string> FeatStrings =
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(*RII)->toFeatures(/* AddAllExtensions */ true);
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Features.insert(Features.end(), FeatStrings.begin(), FeatStrings.end());
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}
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}
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ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef Features) const {
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ParsedTargetAttr Ret;
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if (Features == "default")
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return Ret;
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SmallVector<StringRef, 1> AttrFeatures;
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Features.split(AttrFeatures, ";");
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bool FoundArch = false;
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for (auto &Feature : AttrFeatures) {
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Feature = Feature.trim();
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StringRef AttrString = Feature.split("=").second.trim();
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if (Feature.starts_with("arch=")) {
|
|
// Override last features
|
|
Ret.Features.clear();
|
|
if (FoundArch)
|
|
Ret.Duplicate = "arch=";
|
|
FoundArch = true;
|
|
|
|
if (AttrString.starts_with("+")) {
|
|
// EXTENSION like arch=+v,+zbb
|
|
SmallVector<StringRef, 1> Exts;
|
|
AttrString.split(Exts, ",");
|
|
for (auto Ext : Exts) {
|
|
if (Ext.empty())
|
|
continue;
|
|
|
|
StringRef ExtName = Ext.substr(1);
|
|
std::string TargetFeature =
|
|
llvm::RISCVISAInfo::getTargetFeatureForExtension(ExtName);
|
|
if (!TargetFeature.empty())
|
|
Ret.Features.push_back(Ext.front() + TargetFeature);
|
|
else
|
|
Ret.Features.push_back(Ext.str());
|
|
}
|
|
} else {
|
|
// full-arch-string like arch=rv64gcv
|
|
handleFullArchString(AttrString, Ret.Features);
|
|
}
|
|
} else if (Feature.starts_with("cpu=")) {
|
|
if (!Ret.CPU.empty())
|
|
Ret.Duplicate = "cpu=";
|
|
|
|
Ret.CPU = AttrString;
|
|
|
|
if (!FoundArch) {
|
|
// Update Features with CPU's features
|
|
StringRef MarchFromCPU = llvm::RISCV::getMArchFromMcpu(Ret.CPU);
|
|
if (MarchFromCPU != "") {
|
|
Ret.Features.clear();
|
|
handleFullArchString(MarchFromCPU, Ret.Features);
|
|
}
|
|
}
|
|
} else if (Feature.starts_with("tune=")) {
|
|
if (!Ret.Tune.empty())
|
|
Ret.Duplicate = "tune=";
|
|
|
|
Ret.Tune = AttrString;
|
|
} else if (Feature.starts_with("priority")) {
|
|
// Skip because it only use for FMV.
|
|
}
|
|
}
|
|
return Ret;
|
|
}
|
|
|
|
TargetInfo::CallingConvCheckResult
|
|
RISCVTargetInfo::checkCallingConvention(CallingConv CC) const {
|
|
switch (CC) {
|
|
default:
|
|
return CCCR_Warning;
|
|
case CC_C:
|
|
case CC_RISCVVectorCall:
|
|
return CCCR_OK;
|
|
}
|
|
}
|
|
|
|
bool RISCVTargetInfo::validateCpuSupports(StringRef Feature) const {
|
|
// Only allow extensions we have a known bit position for in the
|
|
// __riscv_feature_bits structure.
|
|
return -1 != llvm::RISCVISAInfo::getRISCVFeaturesBitsInfo(Feature).second;
|
|
}
|
|
|
|
bool RISCVTargetInfo::isValidFeatureName(StringRef Name) const {
|
|
return llvm::RISCVISAInfo::isSupportedExtensionFeature(Name);
|
|
}
|
|
|
|
bool RISCVTargetInfo::validateGlobalRegisterVariable(
|
|
StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const {
|
|
if (RegName == "ra" || RegName == "sp" || RegName == "gp" ||
|
|
RegName == "tp" || RegName.starts_with("x") || RegName.starts_with("a") ||
|
|
RegName.starts_with("s") || RegName.starts_with("t")) {
|
|
unsigned XLen = getTriple().isArch64Bit() ? 64 : 32;
|
|
HasSizeMismatch = RegSize != XLen;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|