04fff547e2
Currently the return address ABI registers s[30:31], which fall in the call clobbered register range, are added as a live-in on the function entry to preserve its value when we have calls so that it gets saved and restored around the calls. But the DWARF unwind information (CFI) needs to track where the return address resides in a frame and the above approach makes it difficult to track the return address when the CFI information is emitted during the frame lowering, due to the involvment of understanding the control flow. This patch moves the return address ABI registers s[30:31] into callee saved registers range and stops adding live-in for return address registers, so that the CFI machinery will know where the return address resides when CSR save/restore happen during the frame lowering. And doing the above poses an issue that now the return instruction uses undefined register `sgpr30_sgpr31`. This is resolved by hiding the return address register use by the return instruction through the `SI_RETURN` pseudo instruction, which doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the `S_SETPC_B64_return` during the `expandPostRAPseudo()`. As an added benefit, this patch simplifies overall return instruction handling. Note: The AMDGPU CFI changes are there only in the downstream code and another version of this patch will be posted for review for the downstream code. Reviewed By: arsenm, ronlieb Differential Revision: https://reviews.llvm.org/D114652
1930 lines
79 KiB
LLVM
1930 lines
79 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s
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define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
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; GCN-LABEL: s_test_udiv_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-NEXT: s_mov_b32 s7, 0xf000
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; GCN-NEXT: s_mov_b32 s6, -1
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8
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; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9
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; GCN-NEXT: s_sub_u32 s4, 0, s8
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; GCN-NEXT: s_subb_u32 s5, 0, s9
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; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
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; GCN-NEXT: v_rcp_f32_e32 v0, v0
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; GCN-NEXT: v_mov_b32_e32 v1, 0
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; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
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; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
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; GCN-NEXT: v_trunc_f32_e32 v2, v2
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; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
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; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
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; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
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; GCN-NEXT: v_mul_lo_u32 v3, s4, v2
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; GCN-NEXT: v_mul_hi_u32 v4, s4, v0
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; GCN-NEXT: v_mul_lo_u32 v6, s5, v0
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; GCN-NEXT: v_mul_lo_u32 v5, s4, v0
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
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; GCN-NEXT: v_mul_hi_u32 v4, v0, v5
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; GCN-NEXT: v_mul_lo_u32 v6, v0, v3
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; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
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; GCN-NEXT: v_mul_lo_u32 v7, v2, v5
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; GCN-NEXT: v_mul_hi_u32 v5, v2, v5
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; GCN-NEXT: v_mul_hi_u32 v9, v2, v3
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
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; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
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; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7
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; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v5, vcc
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; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
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; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
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; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
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; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
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; GCN-NEXT: v_mul_lo_u32 v3, s4, v2
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; GCN-NEXT: v_mul_hi_u32 v4, s4, v0
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; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
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; GCN-NEXT: s_mov_b32 s5, s1
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
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; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
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; GCN-NEXT: v_mul_lo_u32 v7, v0, v3
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; GCN-NEXT: v_mul_hi_u32 v8, v0, v4
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; GCN-NEXT: v_mul_hi_u32 v9, v0, v3
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; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
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; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
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; GCN-NEXT: v_mul_hi_u32 v5, v2, v3
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; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
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; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
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; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
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; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
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; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc
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; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v1, vcc
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
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; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
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; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
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; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
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; GCN-NEXT: v_mul_lo_u32 v3, s2, v2
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; GCN-NEXT: v_mul_hi_u32 v4, s2, v0
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; GCN-NEXT: v_mul_hi_u32 v5, s2, v2
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; GCN-NEXT: v_mul_hi_u32 v6, s3, v2
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; GCN-NEXT: v_mul_lo_u32 v2, s3, v2
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
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; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
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; GCN-NEXT: v_mul_lo_u32 v5, s3, v0
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; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
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; GCN-NEXT: s_mov_b32 s4, s0
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; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
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; GCN-NEXT: v_addc_u32_e32 v0, vcc, v4, v0, vcc
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; GCN-NEXT: v_addc_u32_e32 v1, vcc, v6, v1, vcc
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; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
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; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; GCN-NEXT: v_mul_lo_u32 v2, s8, v1
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; GCN-NEXT: v_mul_hi_u32 v3, s8, v0
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; GCN-NEXT: v_mul_lo_u32 v4, s9, v0
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; GCN-NEXT: v_mov_b32_e32 v5, s9
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; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
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; GCN-NEXT: v_mul_lo_u32 v3, s8, v0
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; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
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; GCN-NEXT: v_sub_i32_e32 v4, vcc, s3, v2
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; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3
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; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc
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; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v3
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; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1]
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; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s9, v4
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; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1]
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; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s8, v5
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; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
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; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s9, v4
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; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1]
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; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0
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; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1]
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; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0
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; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1]
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; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
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; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1]
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; GCN-NEXT: v_mov_b32_e32 v6, s3
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; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc
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; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v2
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; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
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; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v3
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; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
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; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v2
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; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
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; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1]
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; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
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; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GCN-NEXT: s_endpgm
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;
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; GCN-IR-LABEL: s_test_udiv_i64:
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; GCN-IR: ; %bb.0: ; %_udiv-special-cases
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; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
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; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GCN-IR-NEXT: s_mov_b64 s[6:7], 0
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; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[4:5], 0
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; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
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; GCN-IR-NEXT: s_flbit_i32_b32 s12, s4
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; GCN-IR-NEXT: s_add_i32 s12, s12, 32
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; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[10:11]
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; GCN-IR-NEXT: s_flbit_i32_b32 s8, s5
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; GCN-IR-NEXT: s_min_u32 s10, s12, s8
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; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2
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; GCN-IR-NEXT: s_add_i32 s8, s8, 32
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; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3
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; GCN-IR-NEXT: s_min_u32 s12, s8, s9
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; GCN-IR-NEXT: s_sub_u32 s8, s10, s12
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; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
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; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
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; GCN-IR-NEXT: s_mov_b32 s11, 0
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; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
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; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
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; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1
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; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17]
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; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
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; GCN-IR-NEXT: s_cbranch_vccz .LBB0_5
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; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
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; GCN-IR-NEXT: s_add_u32 s14, s8, 1
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
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; GCN-IR-NEXT: s_addc_u32 s15, s9, 0
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; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
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; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
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; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
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; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
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; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[2:3], s8
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; GCN-IR-NEXT: s_cbranch_vccz .LBB0_4
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; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
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; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[2:3], s14
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; GCN-IR-NEXT: s_add_u32 s16, s4, -1
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; GCN-IR-NEXT: s_addc_u32 s17, s5, -1
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; GCN-IR-NEXT: s_not_b64 s[2:3], s[10:11]
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; GCN-IR-NEXT: s_add_u32 s2, s2, s12
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; GCN-IR-NEXT: s_mov_b32 s13, s11
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; GCN-IR-NEXT: s_addc_u32 s3, s3, s11
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; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
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; GCN-IR-NEXT: s_mov_b32 s7, 0
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; GCN-IR-NEXT: .LBB0_3: ; %udiv-do-while
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; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[14:15], 1
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; GCN-IR-NEXT: s_lshr_b32 s6, s9, 31
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; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
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; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[6:7]
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; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
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; GCN-IR-NEXT: s_sub_u32 s6, s16, s12
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; GCN-IR-NEXT: s_subb_u32 s6, s17, s13
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; GCN-IR-NEXT: s_ashr_i32 s10, s6, 31
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; GCN-IR-NEXT: s_mov_b32 s11, s10
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; GCN-IR-NEXT: s_and_b32 s6, s10, 1
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; GCN-IR-NEXT: s_and_b64 s[14:15], s[10:11], s[4:5]
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; GCN-IR-NEXT: s_sub_u32 s14, s12, s14
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
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; GCN-IR-NEXT: s_subb_u32 s15, s13, s15
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; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
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; GCN-IR-NEXT: s_add_u32 s2, s2, 1
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; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
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; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
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; GCN-IR-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GCN-IR-NEXT: s_cbranch_vccz .LBB0_3
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; GCN-IR-NEXT: .LBB0_4: ; %Flow6
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; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
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; GCN-IR-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
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; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
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; GCN-IR-NEXT: s_branch .LBB0_6
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; GCN-IR-NEXT: .LBB0_5:
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
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; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15]
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; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
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; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15]
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; GCN-IR-NEXT: .LBB0_6: ; %udiv-end
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; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
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; GCN-IR-NEXT: s_mov_b32 s2, -1
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; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GCN-IR-NEXT: s_endpgm
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%result = udiv i64 %x, %y
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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define i64 @v_test_udiv_i64(i64 %x, i64 %y) {
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; GCN-LABEL: v_test_udiv_i64:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2
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; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3
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; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2
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; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc
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; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
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; GCN-NEXT: v_rcp_f32_e32 v4, v4
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; GCN-NEXT: v_mov_b32_e32 v13, 0
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; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
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; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
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; GCN-NEXT: v_trunc_f32_e32 v5, v5
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; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5
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; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5
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; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4
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; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
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; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
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; GCN-NEXT: v_mul_lo_u32 v10, v7, v4
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; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
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; GCN-NEXT: v_mul_lo_u32 v9, v6, v4
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; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10
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; GCN-NEXT: v_mul_lo_u32 v10, v4, v8
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; GCN-NEXT: v_mul_hi_u32 v11, v4, v9
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; GCN-NEXT: v_mul_hi_u32 v12, v4, v8
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; GCN-NEXT: v_mul_hi_u32 v14, v5, v8
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; GCN-NEXT: v_mul_lo_u32 v8, v5, v8
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; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
|
|
; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v12, v5, v9
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v5, v9
|
|
; GCN-NEXT: v_add_i32_e32 v10, vcc, v10, v12
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v13, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v8
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v9, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v6, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v6, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v7, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v6, v4
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v4, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v11, v4, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v12, v4, v7
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v5, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v5, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v5, v7
|
|
; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10
|
|
; GCN-NEXT: v_addc_u32_e32 v11, vcc, 0, v12, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v5, v7
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v10, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v0, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v0, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v1, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v1, v5
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v1, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v13, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v2, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v2, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v3, v4
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v2, v4
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
|
|
; GCN-NEXT: v_sub_i32_e32 v8, vcc, v1, v6
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
|
|
; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v8, v3, vcc
|
|
; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v2
|
|
; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3
|
|
; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2
|
|
; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v3
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5]
|
|
; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v4
|
|
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc
|
|
; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
|
|
; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v4
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
|
|
; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, v10, v8, s[4:5]
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v1, v11, v9, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3
|
|
; GCN-IR-NEXT: v_min_u32_e32 v8, v4, v5
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0
|
|
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1
|
|
; GCN-IR-NEXT: v_min_u32_e32 v10, v4, v5
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v8, v10
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[6:7]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7]
|
|
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v11, v9
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5]
|
|
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB1_6
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v6
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v7, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6
|
|
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v6, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB1_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, -1, v2
|
|
; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, -1, v3, vcc
|
|
; GCN-IR-NEXT: v_not_b32_e32 v0, v8
|
|
; GCN-IR-NEXT: v_not_b32_e32 v1, v9
|
|
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v10
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, v1, v11, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
|
|
; GCN-IR-NEXT: .LBB1_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[12:13], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5
|
|
; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6
|
|
; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v14, v10
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v15, v11, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v4, v8, v4
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v6
|
|
; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v8
|
|
; GCN-IR-NEXT: v_and_b32_e32 v13, v8, v3
|
|
; GCN-IR-NEXT: v_and_b32_e32 v12, v8, v2
|
|
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v0
|
|
; GCN-IR-NEXT: v_or_b32_e32 v5, v9, v5
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[0:1]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, v8
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v10, v12
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, v9
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, v7
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v11, v13, s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v8, v6
|
|
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: s_cbranch_execnz .LBB1_3
|
|
; GCN-IR-NEXT: ; %bb.4: ; %Flow
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: .LBB1_5: ; %Flow3
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0
|
|
; GCN-IR-NEXT: .LBB1_6: ; %Flow4
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, v5
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, v4
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = udiv i64 %x, %y
|
|
ret i64 %result
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
|
|
; GCN-LABEL: s_test_udiv24_64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s4, 8
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv24_64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s4, 8
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-IR-NEXT: s_mov_b32 s4, s0
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s5, s1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr i64 %x, 40
|
|
%2 = lshr i64 %y, 40
|
|
%result = udiv i64 %1, %2
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define i64 @v_test_udiv24_i64(i64 %x, i64 %y) {
|
|
; GCN-LABEL: v_test_udiv24_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v1
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv24_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%1 = lshr i64 %x, 40
|
|
%2 = lshr i64 %y, 40
|
|
%result = udiv i64 %1, %2
|
|
ret i64 %result
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
|
|
; GCN-LABEL: s_test_udiv32_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv32_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s3
|
|
; GCN-IR-NEXT: s_mov_b32 s4, s0
|
|
; GCN-IR-NEXT: s_mov_b32 s5, s1
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr i64 %x, 32
|
|
%2 = lshr i64 %y, 32
|
|
%result = udiv i64 %1, %2
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
|
|
; GCN-LABEL: s_test_udiv31_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s4, 1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-NEXT: s_lshr_b32 s2, s3, 1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv31_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s4, 1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-IR-NEXT: s_mov_b32 s4, s0
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s5, s1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr i64 %x, 33
|
|
%2 = lshr i64 %y, 33
|
|
%result = udiv i64 %1, %2
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) {
|
|
; GCN-LABEL: s_test_udiv23_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s4, 9
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-NEXT: s_lshr_b32 s2, s3, 9
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv23_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s4, 9
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 9
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2
|
|
; GCN-IR-NEXT: s_mov_b32 s4, s0
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s5, s1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr i64 %x, 41
|
|
%2 = lshr i64 %y, 41
|
|
%result = udiv i64 %1, %2
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) {
|
|
; GCN-LABEL: s_test_udiv24_i48:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dword s2, s[0:1], 0xe
|
|
; GCN-NEXT: s_load_dword s4, s[0:1], 0xd
|
|
; GCN-NEXT: s_mov_b32 s6, 0xffff
|
|
; GCN-NEXT: s_mov_b32 s7, 0xff000000
|
|
; GCN-NEXT: v_cvt_f32_ubyte3_e32 v2, s6
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_and_b32 s3, s2, s6
|
|
; GCN-NEXT: s_and_b32 s2, s4, s7
|
|
; GCN-NEXT: v_mov_b32_e32 v0, s2
|
|
; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 24
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0
|
|
; GCN-NEXT: s_load_dword s8, s[0:1], 0xb
|
|
; GCN-NEXT: s_load_dword s9, s[0:1], 0xc
|
|
; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
|
; GCN-NEXT: s_lshr_b64 s[0:1], s[2:3], 24
|
|
; GCN-NEXT: v_mac_f32_e32 v1, 0x4f800000, v2
|
|
; GCN-NEXT: v_rcp_f32_e32 v1, v1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_and_b32 s6, s9, s6
|
|
; GCN-NEXT: s_and_b32 s8, s8, s7
|
|
; GCN-NEXT: s_sub_u32 s0, 0, s0
|
|
; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
|
|
; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
|
|
; GCN-NEXT: s_subb_u32 s1, 0, s1
|
|
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
|
; GCN-NEXT: v_mul_hi_u32 v3, s0, v1
|
|
; GCN-NEXT: v_mul_lo_u32 v4, s0, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v5, s1, v1
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, s0, v1
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v1, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v1, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v1, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v2, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v7, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v2, v4
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v4, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v3, s0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v4, s0, v1
|
|
; GCN-NEXT: v_mul_lo_u32 v5, s1, v1
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v4, s0, v1
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v1, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v1, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v1, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v2, v3
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, v9, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v6, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3
|
|
; GCN-NEXT: v_mov_b32_e32 v3, s8
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
|
|
; GCN-NEXT: v_alignbit_b32 v3, s6, v3, 24
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v3, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v1, v3, v1
|
|
; GCN-NEXT: v_mul_hi_u32 v2, v3, v2
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v0, v1
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, 2, v1
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v0, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v10
|
|
; GCN-NEXT: v_subb_u32_e32 v6, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_sub_i32_e32 v7, vcc, v3, v0
|
|
; GCN-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v7, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v0
|
|
; GCN-NEXT: v_cndmask_b32_e32 v7, -1, v7, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v6
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v4, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v5, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1]
|
|
; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
|
|
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv24_i48:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xc
|
|
; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xb
|
|
; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd
|
|
; GCN-IR-NEXT: s_load_dword s7, s[0:1], 0xe
|
|
; GCN-IR-NEXT: s_mov_b32 s8, 0xffff
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_and_b32 s1, s2, s8
|
|
; GCN-IR-NEXT: s_mov_b32 s2, 0xff000000
|
|
; GCN-IR-NEXT: s_and_b32 s0, s3, s2
|
|
; GCN-IR-NEXT: s_and_b32 s3, s7, s8
|
|
; GCN-IR-NEXT: s_and_b32 s2, s6, s2
|
|
; GCN-IR-NEXT: s_lshr_b64 s[6:7], s[0:1], 24
|
|
; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[2:3], 24
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[2:3], 0
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[6:7], 0
|
|
; GCN-IR-NEXT: s_mov_b64 s[0:1], 0
|
|
; GCN-IR-NEXT: s_or_b64 s[14:15], s[8:9], s[10:11]
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s2
|
|
; GCN-IR-NEXT: s_add_i32 s8, s8, 32
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s3
|
|
; GCN-IR-NEXT: s_min_u32 s10, s8, s9
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s8, s6
|
|
; GCN-IR-NEXT: s_add_i32 s8, s8, 32
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s9, s7
|
|
; GCN-IR-NEXT: s_min_u32 s12, s8, s9
|
|
; GCN-IR-NEXT: s_sub_u32 s8, s10, s12
|
|
; GCN-IR-NEXT: s_subb_u32 s9, 0, 0
|
|
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[16:17], s[8:9], 63
|
|
; GCN-IR-NEXT: s_mov_b32 s11, 0
|
|
; GCN-IR-NEXT: s_or_b64 s[14:15], s[14:15], s[16:17]
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[16:17], s[8:9], 63
|
|
; GCN-IR-NEXT: s_xor_b64 s[18:19], s[14:15], -1
|
|
; GCN-IR-NEXT: s_and_b64 s[16:17], s[18:19], s[16:17]
|
|
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[16:17]
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_5
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: s_add_u32 s14, s8, 1
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
|
|
; GCN-IR-NEXT: s_addc_u32 s15, s9, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[14:15], v[0:1]
|
|
; GCN-IR-NEXT: s_sub_i32 s8, 63, s8
|
|
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
|
|
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[6:7], s8
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_4
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: s_lshr_b64 s[14:15], s[6:7], s14
|
|
; GCN-IR-NEXT: s_add_u32 s16, s2, -1
|
|
; GCN-IR-NEXT: s_addc_u32 s17, s3, -1
|
|
; GCN-IR-NEXT: s_not_b64 s[0:1], s[10:11]
|
|
; GCN-IR-NEXT: s_add_u32 s6, s0, s12
|
|
; GCN-IR-NEXT: s_mov_b32 s13, s11
|
|
; GCN-IR-NEXT: s_addc_u32 s7, s1, s11
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
|
|
; GCN-IR-NEXT: s_mov_b32 s1, 0
|
|
; GCN-IR-NEXT: .LBB7_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[14:15], 1
|
|
; GCN-IR-NEXT: s_lshr_b32 s0, s9, 31
|
|
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
|
|
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[0:1]
|
|
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
|
|
; GCN-IR-NEXT: s_sub_u32 s0, s16, s12
|
|
; GCN-IR-NEXT: s_subb_u32 s0, s17, s13
|
|
; GCN-IR-NEXT: s_ashr_i32 s10, s0, 31
|
|
; GCN-IR-NEXT: s_mov_b32 s11, s10
|
|
; GCN-IR-NEXT: s_and_b32 s0, s10, 1
|
|
; GCN-IR-NEXT: s_and_b64 s[14:15], s[10:11], s[2:3]
|
|
; GCN-IR-NEXT: s_sub_u32 s14, s12, s14
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
|
|
; GCN-IR-NEXT: s_subb_u32 s15, s13, s15
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
|
|
; GCN-IR-NEXT: s_add_u32 s6, s6, 1
|
|
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[0:1]
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB7_3
|
|
; GCN-IR-NEXT: .LBB7_4: ; %Flow3
|
|
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
|
|
; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s1
|
|
; GCN-IR-NEXT: s_branch .LBB7_6
|
|
; GCN-IR-NEXT: .LBB7_5:
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s7
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[14:15]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[14:15]
|
|
; GCN-IR-NEXT: .LBB7_6: ; %udiv-end
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4
|
|
; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%1 = lshr i48 %x, 24
|
|
%2 = lshr i48 %y, 24
|
|
%result = udiv i48 %1, %2
|
|
store i48 %result, i48 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_udiv_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3
|
|
; GCN-NEXT: s_sub_u32 s4, 0, s2
|
|
; GCN-NEXT: s_subb_u32 s5, 0, s3
|
|
; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1
|
|
; GCN-NEXT: v_rcp_f32_e32 v0, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v0
|
|
; GCN-NEXT: v_trunc_f32_e32 v2, v2
|
|
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v3, s4, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v4, s4, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v6, s5, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v5, s4, v0
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v0, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v0, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v0, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v2, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v2, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v2, v3
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v8, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v6, v7, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v4, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v3, s4, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v4, s4, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v5, s5, v0
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v4, s4, v0
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v0, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v0, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v2, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v2, v3
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v2, v3
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v6, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v1, 24
|
|
; GCN-NEXT: v_mul_hi_u32 v0, v0, 24
|
|
; GCN-NEXT: v_mul_hi_u32 v1, v1, 24
|
|
; GCN-NEXT: v_mov_b32_e32 v4, s3
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v1, s3, v0
|
|
; GCN-NEXT: v_mul_hi_u32 v2, s2, v0
|
|
; GCN-NEXT: v_add_i32_e32 v1, vcc, v2, v1
|
|
; GCN-NEXT: v_mul_lo_u32 v2, s2, v0
|
|
; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
|
|
; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2
|
|
; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc
|
|
; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v2
|
|
; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]
|
|
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
|
|
; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4
|
|
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v3
|
|
; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1]
|
|
; GCN-NEXT: v_add_i32_e64 v4, s[0:1], 2, v0
|
|
; GCN-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1]
|
|
; GCN-NEXT: v_add_i32_e64 v6, s[0:1], 1, v0
|
|
; GCN-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1]
|
|
; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3
|
|
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v3, v7, v5, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2
|
|
; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v2, v6, v4, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v3, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv_k_num_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
|
|
; GCN-IR-NEXT: s_add_i32 s4, s4, 32
|
|
; GCN-IR-NEXT: s_min_u32 s6, s4, s5
|
|
; GCN-IR-NEXT: s_add_u32 s8, s6, 0xffffffc5
|
|
; GCN-IR-NEXT: s_addc_u32 s9, 0, -1
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
|
|
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[8:9], 63
|
|
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
|
|
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[8:9], 63
|
|
; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
|
|
; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
|
|
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_5
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: s_add_u32 s10, s8, 1
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s8
|
|
; GCN-IR-NEXT: s_addc_u32 s11, s9, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s9
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
|
|
; GCN-IR-NEXT: s_sub_i32 s7, 63, s8
|
|
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
|
|
; GCN-IR-NEXT: s_lshl_b64 s[8:9], 24, s7
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_4
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: s_lshr_b64 s[12:13], 24, s10
|
|
; GCN-IR-NEXT: s_add_u32 s14, s2, -1
|
|
; GCN-IR-NEXT: s_addc_u32 s15, s3, -1
|
|
; GCN-IR-NEXT: s_sub_u32 s6, 58, s6
|
|
; GCN-IR-NEXT: s_subb_u32 s7, 0, 0
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
|
|
; GCN-IR-NEXT: s_mov_b32 s5, 0
|
|
; GCN-IR-NEXT: .LBB8_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: s_lshl_b64 s[12:13], s[12:13], 1
|
|
; GCN-IR-NEXT: s_lshr_b32 s4, s9, 31
|
|
; GCN-IR-NEXT: s_lshl_b64 s[8:9], s[8:9], 1
|
|
; GCN-IR-NEXT: s_or_b64 s[12:13], s[12:13], s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[8:9], s[10:11], s[8:9]
|
|
; GCN-IR-NEXT: s_sub_u32 s4, s14, s12
|
|
; GCN-IR-NEXT: s_subb_u32 s4, s15, s13
|
|
; GCN-IR-NEXT: s_ashr_i32 s10, s4, 31
|
|
; GCN-IR-NEXT: s_mov_b32 s11, s10
|
|
; GCN-IR-NEXT: s_and_b32 s4, s10, 1
|
|
; GCN-IR-NEXT: s_and_b64 s[16:17], s[10:11], s[2:3]
|
|
; GCN-IR-NEXT: s_sub_u32 s12, s12, s16
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
|
|
; GCN-IR-NEXT: s_subb_u32 s13, s13, s17
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
|
|
; GCN-IR-NEXT: s_add_u32 s6, s6, 1
|
|
; GCN-IR-NEXT: s_addc_u32 s7, s7, 0
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[6:7], v[0:1]
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB8_3
|
|
; GCN-IR-NEXT: .LBB8_4: ; %Flow5
|
|
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[8:9], 1
|
|
; GCN-IR-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
|
|
; GCN-IR-NEXT: s_branch .LBB8_6
|
|
; GCN-IR-NEXT: .LBB8_5:
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[10:11]
|
|
; GCN-IR-NEXT: .LBB8_6: ; %udiv-end
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%result = udiv i64 24, %x
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; define i64 @v_test_udiv_k_num_i64(i64 %x) {
|
|
; %result = udiv i64 24, %x
|
|
; ret i64 %result
|
|
; }
|
|
|
|
define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_udiv_pow2_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1
|
|
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0
|
|
; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
|
|
; GCN-NEXT: v_rcp_f32_e32 v2, v2
|
|
; GCN-NEXT: v_mov_b32_e32 v11, 0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
|
|
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v3, v3
|
|
; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v5, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v9, v4, v2
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8
|
|
; GCN-NEXT: v_mul_lo_u32 v7, v2, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v2, v9
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v2, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v12, v3, v6
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v3, v6
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7
|
|
; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v10, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v10, v3, v9
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v3, v9
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v10
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, v8, v9, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v8, vcc, v12, v11, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v4, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v4, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v5, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v4, v2
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v2, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v2, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v3, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v3, v5
|
|
; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8
|
|
; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v3, v5
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v8, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v6, v11, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v3, v5, vcc
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v1, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v0, v2
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v0, v2
|
|
; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v3
|
|
; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0x8000, v4
|
|
; GCN-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v1, vcc
|
|
; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v4, v0
|
|
; GCN-NEXT: v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
|
|
; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[4:5]
|
|
; GCN-NEXT: v_add_i32_e64 v6, s[4:5], 2, v2
|
|
; GCN-NEXT: v_addc_u32_e64 v7, s[4:5], 0, 0, s[4:5]
|
|
; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 1, v2
|
|
; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, 0, s[4:5]
|
|
; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v6, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
|
|
; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
|
|
; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
|
|
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
|
|
; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffd0, v6
|
|
; GCN-IR-NEXT: v_addc_u32_e64 v5, s[6:7], 0, -1, vcc
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1]
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[4:5]
|
|
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v2, s8
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v7, 0
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]
|
|
; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v3, v7
|
|
; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB9_6
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
|
|
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[4:5]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB9_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, -1, v0
|
|
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, -1, v1, vcc
|
|
; GCN-IR-NEXT: v_lshr_b64 v[8:9], s[4:5], v8
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, 47, v6
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v7, vcc, 0, v7, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v11, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: .LBB9_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[8:9], v[8:9], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
|
|
; GCN-IR-NEXT: v_or_b32_e32 v8, v8, v4
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, v12, v8
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, v13, v9, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v10, v2
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v10, 31, v4
|
|
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v10
|
|
; GCN-IR-NEXT: v_and_b32_e32 v14, v10, v1
|
|
; GCN-IR-NEXT: v_and_b32_e32 v15, v10, v0
|
|
; GCN-IR-NEXT: v_add_i32_e32 v10, vcc, 1, v6
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v11, v3
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v11, vcc, 0, v7, vcc
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[10:11], v[6:7]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v6, v10
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v8, s[4:5], v8, v15
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v7, v11
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v11, v5
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v9, s[4:5], v9, v14, s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, v4
|
|
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: s_cbranch_execnz .LBB9_3
|
|
; GCN-IR-NEXT: ; %bb.4: ; %Flow
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: .LBB9_5: ; %Flow3
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v5, v1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v4, v0
|
|
; GCN-IR-NEXT: .LBB9_6: ; %Flow4
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, v3
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = udiv i64 32768, %x
|
|
ret i64 %result
|
|
}
|
|
|
|
define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_udiv_pow2_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 15
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v1, 15, v1
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
|
|
; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
|
|
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v6
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
|
|
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
|
|
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB10_6
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
|
|
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB10_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
|
|
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff
|
|
; GCN-IR-NEXT: .LBB10_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
|
|
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v6
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
|
|
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
|
|
; GCN-IR-NEXT: v_and_b32_e32 v7, 0x8000, v7
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, v9
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, v10
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
|
|
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
|
|
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: s_cbranch_execnz .LBB10_3
|
|
; GCN-IR-NEXT: ; %bb.4: ; %Flow
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: .LBB10_5: ; %Flow3
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
|
|
; GCN-IR-NEXT: .LBB10_6: ; %Flow4
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = udiv i64 %x, 32768
|
|
ret i64 %result
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_udiv_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000
|
|
; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000
|
|
; GCN-NEXT: v_rcp_f32_e32 v0, v0
|
|
; GCN-NEXT: s_movk_i32 s4, 0xffe8
|
|
; GCN-NEXT: v_mov_b32_e32 v7, 0
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: v_mul_hi_u32 v2, v0, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v1, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
|
|
; GCN-NEXT: v_mul_hi_u32 v2, v0, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v1, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v0, s4
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v0, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v8, v1, v2
|
|
; GCN-NEXT: v_mul_lo_u32 v2, v1, v2
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v5, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v1, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v1, v4
|
|
; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v7, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v2, s2, v1
|
|
; GCN-NEXT: v_mul_hi_u32 v3, s2, v0
|
|
; GCN-NEXT: v_mul_hi_u32 v4, s2, v1
|
|
; GCN-NEXT: v_mul_hi_u32 v5, s3, v1
|
|
; GCN-NEXT: v_mul_lo_u32 v1, s3, v1
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v4, s3, v0
|
|
; GCN-NEXT: v_mul_hi_u32 v0, s3, v0
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1
|
|
; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v1, 24
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v0, 24
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, 2, v0
|
|
; GCN-NEXT: v_mul_lo_u32 v8, v0, 24
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, 1, v0
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
|
; GCN-NEXT: v_mov_b32_e32 v5, s3
|
|
; GCN-NEXT: v_sub_i32_e32 v8, vcc, s2, v8
|
|
; GCN-NEXT: v_subb_u32_e32 v4, vcc, v5, v4, vcc
|
|
; GCN-NEXT: v_subrev_i32_e32 v5, vcc, 24, v8
|
|
; GCN-NEXT: v_subbrev_u32_e32 v9, vcc, 0, v4, vcc
|
|
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v5
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
|
|
; GCN-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc
|
|
; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v8
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
|
|
; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4
|
|
; GCN-NEXT: v_cndmask_b32_e64 v4, -1, v5, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4
|
|
; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv_k_den_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s4, s2
|
|
; GCN-IR-NEXT: s_flbit_i32_b32 s5, s3
|
|
; GCN-IR-NEXT: s_add_i32 s4, s4, 32
|
|
; GCN-IR-NEXT: s_min_u32 s8, s4, s5
|
|
; GCN-IR-NEXT: s_sub_u32 s6, 59, s8
|
|
; GCN-IR-NEXT: s_subb_u32 s7, 0, 0
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[10:11], s[2:3], 0
|
|
; GCN-IR-NEXT: v_cmp_gt_u64_e64 s[12:13], s[6:7], 63
|
|
; GCN-IR-NEXT: s_mov_b64 s[4:5], 0
|
|
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[12:13]
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e64 s[12:13], s[6:7], 63
|
|
; GCN-IR-NEXT: s_xor_b64 s[14:15], s[10:11], -1
|
|
; GCN-IR-NEXT: s_and_b64 s[12:13], s[14:15], s[12:13]
|
|
; GCN-IR-NEXT: s_and_b64 vcc, exec, s[12:13]
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_5
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: s_add_u32 s10, s6, 1
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s6
|
|
; GCN-IR-NEXT: s_addc_u32 s11, s7, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s7
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[10:11], v[0:1]
|
|
; GCN-IR-NEXT: s_sub_i32 s6, 63, s6
|
|
; GCN-IR-NEXT: s_andn2_b64 vcc, exec, vcc
|
|
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[2:3], s6
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_4
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: s_lshr_b64 s[10:11], s[2:3], s10
|
|
; GCN-IR-NEXT: s_add_u32 s2, s8, 0xffffffc4
|
|
; GCN-IR-NEXT: s_addc_u32 s3, 0, -1
|
|
; GCN-IR-NEXT: s_mov_b64 s[8:9], 0
|
|
; GCN-IR-NEXT: s_mov_b32 s5, 0
|
|
; GCN-IR-NEXT: .LBB11_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: s_lshl_b64 s[10:11], s[10:11], 1
|
|
; GCN-IR-NEXT: s_lshr_b32 s4, s7, 31
|
|
; GCN-IR-NEXT: s_lshl_b64 s[6:7], s[6:7], 1
|
|
; GCN-IR-NEXT: s_or_b64 s[10:11], s[10:11], s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
|
|
; GCN-IR-NEXT: s_sub_u32 s4, 23, s10
|
|
; GCN-IR-NEXT: s_subb_u32 s4, 0, s11
|
|
; GCN-IR-NEXT: s_ashr_i32 s8, s4, 31
|
|
; GCN-IR-NEXT: s_and_b32 s4, s8, 1
|
|
; GCN-IR-NEXT: s_and_b32 s8, s8, 24
|
|
; GCN-IR-NEXT: s_sub_u32 s10, s10, s8
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
|
|
; GCN-IR-NEXT: s_subb_u32 s11, s11, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
|
|
; GCN-IR-NEXT: s_add_u32 s2, s2, 1
|
|
; GCN-IR-NEXT: s_addc_u32 s3, s3, 0
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, s[2:3], v[0:1]
|
|
; GCN-IR-NEXT: s_mov_b64 s[8:9], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_vccz .LBB11_3
|
|
; GCN-IR-NEXT: .LBB11_4: ; %Flow5
|
|
; GCN-IR-NEXT: s_lshl_b64 s[2:3], s[6:7], 1
|
|
; GCN-IR-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, s3
|
|
; GCN-IR-NEXT: s_branch .LBB11_6
|
|
; GCN-IR-NEXT: .LBB11_5:
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s3
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[10:11]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, s2
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[10:11]
|
|
; GCN-IR-NEXT: .LBB11_6: ; %udiv-end
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%result = udiv i64 %x, 24
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define i64 @v_test_udiv_k_den_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_udiv_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000
|
|
; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000
|
|
; GCN-NEXT: v_rcp_f32_e32 v2, v2
|
|
; GCN-NEXT: s_movk_i32 s4, 0xffe8
|
|
; GCN-NEXT: v_mov_b32_e32 v8, 0
|
|
; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
|
|
; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
|
|
; GCN-NEXT: v_trunc_f32_e32 v3, v3
|
|
; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v2, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v3, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v2, s4
|
|
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v6, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v2, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v9, v3, v5
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v3, v5
|
|
; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v9
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
|
|
; GCN-NEXT: v_mul_hi_u32 v4, v2, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v3, s4
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v2, s4
|
|
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5
|
|
; GCN-NEXT: v_mul_lo_u32 v5, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v2, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v9, v2, v4
|
|
; GCN-NEXT: v_mul_hi_u32 v10, v3, v4
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v3, v4
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5
|
|
; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v9, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v9, v3, v6
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v3, v6
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v0, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v0, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v6, v0, v3
|
|
; GCN-NEXT: v_mul_hi_u32 v7, v1, v3
|
|
; GCN-NEXT: v_mul_lo_u32 v3, v1, v3
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
|
; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v1, v2
|
|
; GCN-NEXT: v_mul_hi_u32 v2, v1, v2
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6
|
|
; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc
|
|
; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v8, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3
|
|
; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc
|
|
; GCN-NEXT: v_mul_lo_u32 v4, v3, 24
|
|
; GCN-NEXT: v_mul_hi_u32 v5, v2, 24
|
|
; GCN-NEXT: v_mul_lo_u32 v6, v2, 24
|
|
; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4
|
|
; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
|
|
; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc
|
|
; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v0
|
|
; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v1, vcc
|
|
; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v4
|
|
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
|
|
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
|
|
; GCN-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v2
|
|
; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v2
|
|
; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], 23, v0
|
|
; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5]
|
|
; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
|
|
; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc
|
|
; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
|
|
; GCN-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc
|
|
; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5]
|
|
; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5]
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv_k_den_i64:
|
|
; GCN-IR: ; %bb.0: ; %_udiv-special-cases
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0
|
|
; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2
|
|
; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1
|
|
; GCN-IR-NEXT: v_min_u32_e32 v6, v2, v3
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 59, v6
|
|
; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
|
|
; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5]
|
|
; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5]
|
|
; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5]
|
|
; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB12_6
|
|
; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1
|
|
; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4
|
|
; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v4, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: s_mov_b64 s[10:11], 0
|
|
; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc
|
|
; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5]
|
|
; GCN-IR-NEXT: s_cbranch_execz .LBB12_5
|
|
; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader
|
|
; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7
|
|
; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, 0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v5, 0
|
|
; GCN-IR-NEXT: .LBB12_3: ; %udiv-do-while
|
|
; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1
|
|
; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3
|
|
; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4
|
|
; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1
|
|
; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6
|
|
; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2
|
|
; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3
|
|
; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7
|
|
; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7
|
|
; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, v9
|
|
; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, v10
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v10, v5
|
|
; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5]
|
|
; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v9, v4
|
|
; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: s_cbranch_execnz .LBB12_3
|
|
; GCN-IR-NEXT: ; %bb.4: ; %Flow
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11]
|
|
; GCN-IR-NEXT: .LBB12_5: ; %Flow3
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9]
|
|
; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1
|
|
; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0
|
|
; GCN-IR-NEXT: .LBB12_6: ; %Flow4
|
|
; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7]
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v0, v3
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, v2
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%result = udiv i64 %x, 24
|
|
ret i64 %result
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_udiv24_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s4, 0x41c00000
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s2, -1
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv24_k_num_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-IR-NEXT: s_mov_b32 s3, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s2, -1
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = udiv i64 24, %x.shr
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) {
|
|
; GCN-LABEL: s_test_udiv24_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-NEXT: s_mov_b32 s6, -1
|
|
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00
|
|
; GCN-NEXT: s_mov_b32 s4, s0
|
|
; GCN-NEXT: s_mov_b32 s5, s1
|
|
; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-NEXT: s_endpgm
|
|
;
|
|
; GCN-IR-LABEL: s_test_udiv24_k_den_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
; GCN-IR-NEXT: s_mov_b32 s7, 0xf000
|
|
; GCN-IR-NEXT: s_mov_b32 s6, -1
|
|
; GCN-IR-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2
|
|
; GCN-IR-NEXT: s_mov_b32 s2, 0x46b6fe00
|
|
; GCN-IR-NEXT: s_mov_b32 s4, s0
|
|
; GCN-IR-NEXT: s_mov_b32 s5, s1
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mad_f32 v0, -v1, s2, v0
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GCN-IR-NEXT: s_endpgm
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = udiv i64 %x.shr, 23423
|
|
store i64 %result, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
define i64 @v_test_udiv24_k_num_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_udiv24_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
; GCN-NEXT: s_mov_b32 s4, 0x41c00000
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv24_k_num_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = udiv i64 24, %x.shr
|
|
ret i64 %result
|
|
}
|
|
|
|
define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_udiv24_pow2_k_num_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
; GCN-NEXT: s_mov_b32 s4, 0x47000000
|
|
; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-NEXT: v_mul_f32_e32 v1, s4, v1
|
|
; GCN-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4
|
|
; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
|
|
; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = udiv i64 32768, %x.shr
|
|
ret i64 %result
|
|
}
|
|
|
|
define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) {
|
|
; GCN-LABEL: v_test_udiv24_pow2_k_den_i64:
|
|
; GCN: ; %bb.0:
|
|
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-NEXT: v_lshrrev_b32_e32 v0, 23, v1
|
|
; GCN-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64:
|
|
; GCN-IR: ; %bb.0:
|
|
; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1
|
|
; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0
|
|
; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000
|
|
; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38000000, v0
|
|
; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1
|
|
; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1
|
|
; GCN-IR-NEXT: v_mad_f32 v0, -v1, s4, v0
|
|
; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
|
|
; GCN-IR-NEXT: v_mov_b32_e32 v1, 0
|
|
; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
|
|
; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0
|
|
; GCN-IR-NEXT: s_setpc_b64 s[30:31]
|
|
%x.shr = lshr i64 %x, 40
|
|
%result = udiv i64 %x.shr, 32768
|
|
ret i64 %result
|
|
}
|