Pierre van Houtryve 4e63e0457c

[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792) ...

Canonicalize it to a G_AND instead so that ISel patterns can pick it
up and ignore it, as the shift instructions only read low bits.
G_ZEXT would be lowered to a v/s_and anyway in most cases.

I'm also looking at making a DAG version of this in a separate patch.

2025-05-14 10:48:51 +02:00

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AArch64

[DAG] visitINSERT_VECTOR_ELT - convert to or mask if all insertions are -1 (#138213)

2025-05-13 17:10:54 +01:00

AMDGPU

[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792)

2025-05-14 10:48:51 +02:00

ARC

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ARM

[DAG] Add SDPatternMatch::m_BitwiseLogic common matcher for AND/OR/XOR nodes (#138301)

2025-05-06 12:50:50 +01:00

AVR

[clang][AVR] Improve compatibility of inline assembly with avr-gcc (#136534)

2025-04-23 18:42:07 +08:00

BPF

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CSKY

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DirectX

[DirectX] Move DXIL Resource Access Pass before Intrinsic Expansion Pass (#139562)

2025-05-13 15:05:01 -07:00

Generic

[LLVM][VecLib] Refactor LIBMVEC integration to be target neutral. (#138262)

2025-05-07 11:05:25 +01:00

Hexagon

Hexagon: sfmax/sfmin instructions are IEEE754-2019 (#139056)

2025-05-14 11:55:11 +08:00

Inputs

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Lanai

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LoongArch

LoongArch: Set FMAXNUM and FMINNUM as Legal (#139010)

2025-05-09 16:26:08 +08:00

M68k

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Mips

MIPSr6: Set FMAXNUM and FMINNUM as Legal (#139009)

2025-05-09 07:40:02 +08:00

MIR

[NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (#139292)

2025-05-13 13:36:09 -07:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Vectorize and lower 256-bit global loads/stores for sm_100+/ptx88+ (#139292)

2025-05-13 13:36:09 -07:00

PowerPC

[PowerPC] catch v2i64 shift left by 1 is add case (#138772)

2025-05-13 11:26:46 -04:00

RISCV

[RISCV] Emit .note.gnu.property section when Zicfiss-based shadow stack is enabled (#127036)

2025-05-14 11:48:59 +08:00

SPARC

[SPARC] Use op-then-neg instructions when we have VIS3 (#138603)

2025-05-06 05:36:29 +07:00

SPIRV

[SPIRV] Reapply explicit layout PRs (#138867)

2025-05-07 13:27:28 -04:00

SystemZ

[MCP] Disable BackwardCopyPropagateBlock for copies with implicit registers. (#137687)

2025-05-08 16:27:08 -07:00

Thumb

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Thumb2

[DAGCombiner] Eliminate fp casts if we have the right fast math flags (#131345)

2025-04-28 11:21:51 +01:00

VE

Reland [SelectionDAG] Folding ZERO-EXTEND/SIGN_EXTEND poison to Poison value in getNode (#136701)

2025-04-22 17:36:41 -04:00

WebAssembly

[WebAssembly] Fix trunc in FastISel (#138479)

2025-05-06 14:16:35 -07:00

WinCFGuard

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WinEH

[WinEH] Fix asm in catchpad being turned into unreachable (#138392)

2025-05-08 21:46:51 +02:00

X86

[X86] isel-brcond-icmp.ll - regenerate checks and add missing X86 test coverage

2025-05-13 17:15:54 +01:00

XCore

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Xtensa

[Xtensa] Implement Xtensa Mul and Div Options. (#132157)

2025-04-18 20:22:03 +03:00