llvm-project

AsmParser

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287 )

2024-07-11 20:12:17 -07:00

Disassembler

[RISCV] Add QingKe "XW" compressed opcode extension (#97925 )

2024-07-11 11:10:02 +08:00

GISel

[RISCV][GISel] Slightly simplify the regbank selection for G_LOAD/STORE. NFC (#101431 )

2024-07-31 19:01:45 -07:00

MCA

[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc

2024-04-24 09:29:20 -07:00

MCTargetDesc

[MC] Forward declare ELFObjectWriter (#100989 )

2024-07-30 10:40:40 +03:00

TargetInfo

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CMakeLists.txt

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800 )

2024-07-11 14:22:00 +08:00

RISCV.h

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800 )

2024-07-11 14:22:00 +08:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR3 (#95427 )

2024-06-25 11:34:59 +03:00

RISCVAsmPrinter.cpp

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329 )

2024-08-01 09:37:42 +08:00

RISCVCombine.td

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RISCVDeadRegisterDefinitions.cpp

[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118 )

2024-07-10 19:34:48 +08:00

RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954 )

2024-04-16 15:40:32 -07:00

RISCVFeatures.td

[RISCV] Rename hasVInstructionsBF16 to hasVInstructionsBF16Minimal. NFC (#101080 )

2024-07-29 21:55:42 -07:00

RISCVFrameLowering.cpp

[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455 )

2024-07-29 11:03:07 +08:00

RISCVFrameLowering.h

[RISCV] Add CFI information for vector callee-saved registers (#86811 )

2024-04-17 10:42:40 +08:00

RISCVGatherScatterLowering.cpp

[llvm] Make InstSimplifyFolder constructor explicit (NFC) (#101654 )

2024-08-02 16:45:50 +03:00

RISCVGISel.td

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RISCVInsertReadWriteCSR.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVInsertVSETVLI.cpp

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVInsertWriteVXRM.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVInstrFormats.td

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RISCVInstrFormatsC.td

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RISCVInstrFormatsV.td

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RISCVInstrGISel.td

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RISCVInstrInfo.cpp

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873 )

2024-08-01 12:24:25 +08:00

RISCVInstrInfo.h

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873 )

2024-08-01 12:24:25 +08:00

RISCVInstrInfo.td

[RISCV] Remove registers from ins of Priv instructions. (#100857 )

2024-07-29 09:09:00 -07:00

RISCVInstrInfoA.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845 )

2024-06-13 11:52:22 +02:00

RISCVInstrInfoC.td

[RISCV] Fix InsnCI register type (#100113 )

2024-07-23 21:19:57 +08:00

RISCVInstrInfoD.td

[RISCV][ISel] Fold FSGNJX idioms (#100718 )

2024-07-27 12:51:58 +08:00

RISCVInstrInfoF.td

[RISCV][ISel] Fold FSGNJX idioms (#100718 )

2024-07-27 12:51:58 +08:00

RISCVInstrInfoM.td

[RISCV] Make M imply Zmmul (#95070 )

2024-06-21 11:11:10 +08:00

RISCVInstrInfoSFB.td

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RISCVInstrInfoV.td

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Support f16 vmv.v.v and vmerge.vvm intrinsics with Zvfhmin. (#101457 )

2024-08-01 08:36:00 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Rename hasVInstructionsBF16 to hasVInstructionsBF16Minimal. NFC (#101080 )

2024-07-29 21:55:42 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Add back missing vmv_v_x_vl pattern predicates (#101455 )

2024-08-01 15:25:36 +08:00

RISCVInstrInfoXCV.td

[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112 )

2024-07-15 10:25:25 +10:00

RISCVInstrInfoXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966 )

2024-05-08 10:13:01 -07:00

RISCVInstrInfoXVentana.td

[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891 )

2024-07-27 17:26:32 -07:00

RISCVInstrInfoXwch.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925 )

2024-07-11 11:10:02 +08:00

RISCVInstrInfoZa.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845 )

2024-06-13 11:52:22 +02:00

RISCVInstrInfoZalasr.td

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RISCVInstrInfoZb.td

[RISCV] Rework zext.h handling for Zbkb again. (#96957 )

2024-06-27 21:35:33 -07:00

RISCVInstrInfoZc.td

[RISCV] Make M imply Zmmul (#95070 )

2024-06-21 11:11:10 +08:00

RISCVInstrInfoZcmop.td

[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826 )

2024-04-15 22:33:14 -07:00

RISCVInstrInfoZfa.td

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RISCVInstrInfoZfbfmin.td

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RISCVInstrInfoZfh.td

[RISCV][ISel] Fold FSGNJX idioms (#100718 )

2024-07-27 12:51:58 +08:00

RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

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RISCVInstrInfoZicond.td

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RISCVInstrInfoZimop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

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RISCVInstrInfoZvk.td

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVISelDAGToDAG.cpp

[RISCV] Fix vmerge.vvm/vmv.v.v getting folded into ops with mismatching EEW (#101152 )

2024-07-31 00:28:52 +08:00

RISCVISelDAGToDAG.h

[RISCV] Codegen support for XCVmem extension (#76916 )

2024-06-07 21:45:49 +08:00

RISCVISelLowering.cpp

[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall (#99752 )

2024-08-02 12:29:39 +03:00

RISCVISelLowering.h

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

[llvm-project] Fix typo "seperate" (#95373 )

2024-06-13 20:20:27 +01:00

RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

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RISCVMergeBaseOffset.cpp

[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790 )

2024-07-26 17:11:01 -07:00

RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968 )

2024-04-24 14:24:14 +01:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Remove unneeded code from RISCVPostRAExpandPseudo::expandMovImm. NFC

2024-06-27 18:42:27 -07:00

RISCVProcessors.td

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873 )

2024-08-01 12:24:25 +08:00

RISCVProfiles.td

[RISCV] Gate unratified profiles behind -menable-experimental-extensions (#92167 )

2024-05-15 21:09:43 +01:00

RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

[RISCV] Codegen support for XCVbi extension (#89719 )

2024-05-08 11:22:16 +08:00

RISCVRegisterInfo.cpp

[RISCV] Mark all registers marked isConstant as reserved (#96002 )

2024-06-23 15:44:41 -07:00

RISCVRegisterInfo.h

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RISCVRegisterInfo.td

[RISCV] Use software guarded branch for indirect jump table branch. (#66762 )

2024-05-14 14:44:25 +08:00

RISCVSchedRocket.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedSiFive7.td

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVSchedSiFiveP400.td

[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735 )

2024-05-30 08:47:27 -07:00

RISCVSchedSiFiveP600.td

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVSchedSyntacoreSCR1.td

[RISCV][NFC] Cleanup SCR1 sched model (#96088 )

2024-06-20 18:14:09 +03:00

RISCVSchedSyntacoreSCR3.td

[RISCV] Add scheduling model for Syntacore SCR3 (#95427 )

2024-06-25 11:34:59 +03:00

RISCVSchedule.td

[RISCV][NFC] Add UnsupportedSched<F|D|A> multiclasses (#95948 )

2024-06-19 12:37:47 +03:00

RISCVScheduleV.td

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00

RISCVScheduleXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093 )

2024-04-16 13:55:45 +08:00

RISCVScheduleZb.td

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RISCVScheduleZvk.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add Sched classes for vector crypto instructions (#90068 )

2024-05-03 11:11:29 -04:00

RISCVSubtarget.cpp

[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC (#98375 )

2024-07-10 14:17:56 -07:00

RISCVSubtarget.h

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873 )

2024-08-01 12:24:25 +08:00

RISCVSystemOperands.td

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287 )

2024-07-11 20:12:17 -07:00

RISCVTargetMachine.cpp

[CodeGen] change prototype of regalloc filter function (#93525 )

2024-07-22 16:49:39 +05:30

RISCVTargetMachine.h

[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082 )

2024-07-02 18:48:28 -07:00

RISCVTargetObjectFile.cpp

[IR] Don't include Module.h in Analysis.h (NFC) (#97023 )

2024-06-28 14:30:47 +02:00

RISCVTargetObjectFile.h

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RISCVTargetTransformInfo.cpp

[RISCV] Qualify all XCV predicates with !is64Bit. (#101074 )

2024-07-29 21:52:57 -07:00

RISCVTargetTransformInfo.h

Revert "[RISCV] Enable TTI::shouldDropLSRSolutionIfLessProfitable by default" (#98328 )

2024-07-10 15:33:20 +01:00

RISCVVectorPeephole.cpp

[RISCV] Rename merge operand -> passthru. NFC (#100330 )

2024-07-30 17:47:00 +08:00