Simon Pilgrim 4e9b9cbee9 [X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets ...

Use 512-bit instructions with subvector insertion/extraction like we do in a number of similar circumstances

llvm-svn: 287762

2016-11-23 14:01:18 +00:00

..

AArch64

[SLP] Avoid signed integer overflow

2016-08-23 20:48:50 +00:00

AMDGPU

[SLPVectorizer] Try different vectorization factors for store chains

2015-07-08 23:40:55 +00:00

ARM

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00

PowerPC

[SLP] Pass in correct alignment when query memory access cost

2016-05-31 20:41:19 +00:00

X86

[X86][AVX512] Add support for v4i64 fptosi/fptoui/sitofp/uitofp on AVX512DQ-only targets

2016-11-23 14:01:18 +00:00

XCore

[opaque pointer type] Add textual IR support for explicit type parameter to load instruction

2015-02-27 21:17:42 +00:00