4ea121c904
There are a few issues with the code we generate for atomic operations and the way we generate it: - Hard coded CR0 for compares - Order of operands for compares not conducive to emitting compare-immediate or for CSE of compares - Missing MachineMemOperand for st[bhwd]cx intrinsics - Missing intrinsic properties for the same - Unnecessary blocks with store conditional instructions to clear reservation (which ends up hindering performance) - Move from CR instructions just to compare the result of a store conditional with zero (even though it is a record-form) This patch aims to resolve all of those issues. Differential revision: https://reviews.llvm.org/D134783
27 lines
759 B
LLVM
27 lines
759 B
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s
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define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
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; CHECK-LABEL: exchange_and_add:
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; CHECK: lwarx {{[0-9]+}}, 0, {{[0-9]+}}
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%tmp = atomicrmw add i32* %mem, i32 %val monotonic
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; CHECK: stwcx. {{[0-9]+}}, 0, {{[0-9]+}}
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ret i32 %tmp
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}
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define i32 @exchange_and_cmp(i32* %mem) nounwind {
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; CHECK-LABEL: exchange_and_cmp:
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; CHECK: lwarx
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%tmppair = cmpxchg i32* %mem, i32 0, i32 1 monotonic monotonic
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%tmp = extractvalue { i32, i1 } %tmppair, 0
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; CHECK: stwcx.
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ret i32 %tmp
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}
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define i32 @exchange(i32* %mem, i32 %val) nounwind {
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; CHECK-LABEL: exchange:
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; CHECK: lwarx
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%tmp = atomicrmw xchg i32* %mem, i32 1 monotonic
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; CHECK: stwcx.
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ret i32 %tmp
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}
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