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llvm-project/llvm/test/CodeGen
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David Green 4ece4cd77e [ARM] Fold away CMP/CSINC from CMOV 
This makes use of the code in D114013 to fold away unnecessary
CMPZ/CSINC starting from a CMOV, in a similar way to how we fold away
CSINV/CSINC/etc

Differential Revision: https://reviews.llvm.org/D115185
2021-12-19 21:53:50 +00:00
..
AArch64
[DAG] Improve FMINNUM/FMAXNUM/FMINIMUM/FMAXIMUM constant folding
2021-12-19 11:45:51 +00:00
AMDGPU
AMDGPU: Regenerate more mir test checks with -NEXT
2021-12-18 11:38:30 -05:00
ARC
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ARM
[ARM] Add AddrModeT2_i8neg addressing mode support for frame lowering.
2021-12-14 12:49:27 +00:00
AVR
[asm] Remove explicit branch for modifier 'l'
2021-11-19 09:19:53 -05:00
BPF
BPF: Workaround InstCombine trunc+icmp => mask+icmp Optimization
2021-11-18 20:25:28 -08:00
CSKY
[CSKY] Complete codegen of basic arithmetic and load/store operations
2021-12-09 11:40:20 +08:00
Generic
[NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis
2021-12-16 17:56:46 -08:00
Hexagon
Reapply [xray] add support for hexagon
2021-12-10 05:32:28 -08:00
Inputs
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Lanai
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M68k
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Mips
[MIPS] Allow i1 values for 'r' constraint in inline-asm
2021-12-14 01:19:34 +03:00
MIR
AMDGPU: Enable fixed function ABI by default
2021-12-04 10:49:18 -05:00
MLRegalloc
[NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis
2021-12-16 17:56:46 -08:00
MSP430
[llvm-readobj] Support dumping of MSP430 ELF attributes
2021-09-28 00:56:11 +03:00
NVPTX
[NVPTX] Auto-generate tests for sufrace and texture instructions
2021-12-07 15:27:51 +03:00
PowerPC
[NFC][regalloc] Introduce the RegAllocEvictionAdvisorAnalysis
2021-12-16 17:56:46 -08:00
RISCV
[DAGCombiner] Avoid combining adjacent stores at -O0 to improve debug experience
2021-12-19 20:58:49 +05:30
SPARC
[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers
2021-11-14 19:59:52 +01:00
SystemZ
[z/OS] Implement prologue and epilogue generation for z/OS target.
2021-12-16 09:04:05 -05:00
Thumb
[clang][ARM] PACBTI-M assembly support
2021-11-30 09:28:18 +00:00
Thumb2
[ARM] Fold away CMP/CSINC from CMOV
2021-12-19 21:53:50 +00:00
VE
[VE] SHL,SRA,SRL v256i32|64 isel and tests
2021-12-15 11:32:18 +01:00
WebAssembly
[WebAssembly] Add simd-vector-trunc.ll test missing from 2a4a229
2021-12-15 09:22:40 -08:00
WinCFGuard
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WinEH
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X86
[SDAG] remove FP-to-int cast attribute check in fold to FTRUNC
2021-12-17 16:01:37 -05:00
XCore
…