e9c49901a4
Uniformity analysis needs to be the fundamental basis for regbank decisions. The considerations of the default pass are secondary, but potentially useful for some edge cases (e.g. selecting AGPRs when arbitrary loads and stores can directly use them). This needs to be a separate pass since it requires new analysis dependencies. Boilerplate to subclass the existing pass which does nothing different.
75 lines
2.6 KiB
C++
75 lines
2.6 KiB
C++
//===- AMDGPURegBankSelect.cpp -----------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Use MachineUniformityAnalysis as the primary basis for making SGPR vs. VGPR
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// register bank selection. Use/def analysis as in the default RegBankSelect can
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// be useful in narrower circumstances (e.g. choosing AGPR vs. VGPR for gfx908).
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPURegBankSelect.h"
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#include "AMDGPU.h"
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#include "llvm/CodeGen/MachineUniformityAnalysis.h"
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#include "llvm/InitializePasses.h"
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#define DEBUG_TYPE "regbankselect"
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using namespace llvm;
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AMDGPURegBankSelect::AMDGPURegBankSelect(Mode RunningMode)
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: RegBankSelect(AMDGPURegBankSelect::ID, RunningMode) {}
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char AMDGPURegBankSelect::ID = 0;
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StringRef AMDGPURegBankSelect::getPassName() const {
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return "AMDGPURegBankSelect";
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}
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void AMDGPURegBankSelect::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineCycleInfoWrapperPass>();
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AU.addRequired<MachineDominatorTree>();
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// TODO: Preserve DomTree
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RegBankSelect::getAnalysisUsage(AU);
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}
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INITIALIZE_PASS_BEGIN(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE,
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"AMDGPU Register Bank Select", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_END(AMDGPURegBankSelect, "amdgpu-" DEBUG_TYPE,
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"AMDGPU Register Bank Select", false, false)
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bool AMDGPURegBankSelect::runOnMachineFunction(MachineFunction &MF) {
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// If the ISel pipeline failed, do not bother running that pass.
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
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const Function &F = MF.getFunction();
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Mode SaveOptMode = OptMode;
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if (F.hasOptNone())
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OptMode = Mode::Fast;
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init(MF);
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assert(checkFunctionIsLegal(MF));
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MachineCycleInfo &CycleInfo =
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getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo();
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MachineDominatorTree &DomTree = getAnalysis<MachineDominatorTree>();
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MachineUniformityInfo Uniformity =
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computeMachineUniformityInfo(MF, CycleInfo, DomTree.getBase());
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(void)Uniformity; // TODO: Use this
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assignRegisterBanks(MF);
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OptMode = SaveOptMode;
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return false;
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}
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