8f6c47b7a4
The function makes liveness tests for the entire live register set for every instruction it passes by. This becomes very slow on high RP regions such as ASAN enabled code. Instead only uses of last tracked instruction should be tested and this greatly improves compilation time. This patch revealed few bugs in SIFormMemoryClauses and PreRARematStage::sinkTriviallyRematInsts which should be fixed first. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D136267
490 lines
16 KiB
C++
490 lines
16 KiB
C++
//===- GCNRegPressure.cpp -------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the GCNRegPressure class.
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///
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//===----------------------------------------------------------------------===//
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#include "GCNRegPressure.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-scheduler"
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bool llvm::isEqual(const GCNRPTracker::LiveRegSet &S1,
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const GCNRPTracker::LiveRegSet &S2) {
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if (S1.size() != S2.size())
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return false;
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for (const auto &P : S1) {
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auto I = S2.find(P.first);
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if (I == S2.end() || I->second != P.second)
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return false;
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}
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return true;
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}
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///////////////////////////////////////////////////////////////////////////////
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// GCNRegPressure
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unsigned GCNRegPressure::getRegKind(Register Reg,
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const MachineRegisterInfo &MRI) {
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assert(Reg.isVirtual());
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const auto RC = MRI.getRegClass(Reg);
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auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
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return STI->isSGPRClass(RC)
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? (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE)
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: STI->isAGPRClass(RC)
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? (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE)
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: (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
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}
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void GCNRegPressure::inc(unsigned Reg,
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LaneBitmask PrevMask,
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LaneBitmask NewMask,
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const MachineRegisterInfo &MRI) {
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if (SIRegisterInfo::getNumCoveredRegs(NewMask) ==
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SIRegisterInfo::getNumCoveredRegs(PrevMask))
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return;
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int Sign = 1;
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if (NewMask < PrevMask) {
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std::swap(NewMask, PrevMask);
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Sign = -1;
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}
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switch (auto Kind = getRegKind(Reg, MRI)) {
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case SGPR32:
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case VGPR32:
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case AGPR32:
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Value[Kind] += Sign;
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break;
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case SGPR_TUPLE:
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case VGPR_TUPLE:
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case AGPR_TUPLE:
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assert(PrevMask < NewMask);
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Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] +=
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Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask);
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if (PrevMask.none()) {
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assert(NewMask.any());
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Value[Kind] += Sign * MRI.getPressureSets(Reg).getWeight();
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}
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break;
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default: llvm_unreachable("Unknown register kind");
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}
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}
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bool GCNRegPressure::less(const GCNSubtarget &ST,
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const GCNRegPressure& O,
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unsigned MaxOccupancy) const {
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const auto SGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(getSGPRNum()));
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const auto VGPROcc =
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std::min(MaxOccupancy,
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ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
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const auto OtherSGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(O.getSGPRNum()));
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const auto OtherVGPROcc =
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std::min(MaxOccupancy,
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ST.getOccupancyWithNumVGPRs(O.getVGPRNum(ST.hasGFX90AInsts())));
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const auto Occ = std::min(SGPROcc, VGPROcc);
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const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
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if (Occ != OtherOcc)
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return Occ > OtherOcc;
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bool SGPRImportant = SGPROcc < VGPROcc;
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const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
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// if both pressures disagree on what is more important compare vgprs
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if (SGPRImportant != OtherSGPRImportant) {
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SGPRImportant = false;
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}
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// compare large regs pressure
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bool SGPRFirst = SGPRImportant;
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for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
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if (SGPRFirst) {
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auto SW = getSGPRTuplesWeight();
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auto OtherSW = O.getSGPRTuplesWeight();
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if (SW != OtherSW)
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return SW < OtherSW;
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} else {
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auto VW = getVGPRTuplesWeight();
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auto OtherVW = O.getVGPRTuplesWeight();
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if (VW != OtherVW)
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return VW < OtherVW;
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}
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}
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return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
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(getVGPRNum(ST.hasGFX90AInsts()) <
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O.getVGPRNum(ST.hasGFX90AInsts()));
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD
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Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST) {
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return Printable([&RP, ST](raw_ostream &OS) {
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OS << "VGPRs: " << RP.Value[GCNRegPressure::VGPR32] << ' '
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<< "AGPRs: " << RP.getAGPRNum();
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if (ST)
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OS << "(O"
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<< ST->getOccupancyWithNumVGPRs(RP.getVGPRNum(ST->hasGFX90AInsts()))
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<< ')';
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OS << ", SGPRs: " << RP.getSGPRNum();
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if (ST)
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OS << "(O" << ST->getOccupancyWithNumSGPRs(RP.getSGPRNum()) << ')';
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OS << ", LVGPR WT: " << RP.getVGPRTuplesWeight()
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<< ", LSGPR WT: " << RP.getSGPRTuplesWeight();
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if (ST)
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OS << " -> Occ: " << RP.getOccupancy(*ST);
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OS << '\n';
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});
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}
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#endif
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static LaneBitmask getDefRegMask(const MachineOperand &MO,
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const MachineRegisterInfo &MRI) {
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assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual());
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// We don't rely on read-undef flag because in case of tentative schedule
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// tracking it isn't set correctly yet. This works correctly however since
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// use mask has been tracked before using LIS.
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return MO.getSubReg() == 0 ?
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MRI.getMaxLaneMaskForVReg(MO.getReg()) :
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MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg());
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}
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static LaneBitmask getUsedRegMask(const MachineOperand &MO,
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const MachineRegisterInfo &MRI,
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const LiveIntervals &LIS) {
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assert(MO.isUse() && MO.isReg() && MO.getReg().isVirtual());
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if (auto SubReg = MO.getSubReg())
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return MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(SubReg);
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auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
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if (SIRegisterInfo::getNumCoveredRegs(MaxMask) > 1) // cannot have subregs
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return MaxMask;
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// For a tentative schedule LIS isn't updated yet but livemask should remain
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// the same on any schedule. Subreg defs can be reordered but they all must
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// dominate uses anyway.
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auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
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return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
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}
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static SmallVector<RegisterMaskPair, 8>
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collectVirtualRegUses(const MachineInstr &MI, const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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SmallVector<RegisterMaskPair, 8> Res;
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for (const auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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if (!MO.isUse() || !MO.readsReg())
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continue;
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auto const UsedMask = getUsedRegMask(MO, MRI, LIS);
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auto Reg = MO.getReg();
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auto I = llvm::find_if(
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Res, [Reg](const RegisterMaskPair &RM) { return RM.RegUnit == Reg; });
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if (I != Res.end())
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I->LaneMask |= UsedMask;
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else
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Res.push_back(RegisterMaskPair(Reg, UsedMask));
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}
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return Res;
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}
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///////////////////////////////////////////////////////////////////////////////
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// GCNRPTracker
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LaneBitmask llvm::getLiveLaneMask(unsigned Reg,
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SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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LaneBitmask LiveMask;
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const auto &LI = LIS.getInterval(Reg);
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if (LI.hasSubRanges()) {
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for (const auto &S : LI.subranges())
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if (S.liveAt(SI)) {
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LiveMask |= S.LaneMask;
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assert(LiveMask < MRI.getMaxLaneMaskForVReg(Reg) ||
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LiveMask == MRI.getMaxLaneMaskForVReg(Reg));
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}
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} else if (LI.liveAt(SI)) {
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LiveMask = MRI.getMaxLaneMaskForVReg(Reg);
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}
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return LiveMask;
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}
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GCNRPTracker::LiveRegSet llvm::getLiveRegs(SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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GCNRPTracker::LiveRegSet LiveRegs;
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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auto Reg = Register::index2VirtReg(I);
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if (!LIS.hasInterval(Reg))
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continue;
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auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
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if (LiveMask.any())
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LiveRegs[Reg] = LiveMask;
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}
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return LiveRegs;
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}
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void GCNRPTracker::reset(const MachineInstr &MI,
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const LiveRegSet *LiveRegsCopy,
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bool After) {
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const MachineFunction &MF = *MI.getMF();
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MRI = &MF.getRegInfo();
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if (LiveRegsCopy) {
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if (&LiveRegs != LiveRegsCopy)
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LiveRegs = *LiveRegsCopy;
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} else {
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LiveRegs = After ? getLiveRegsAfter(MI, LIS)
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: getLiveRegsBefore(MI, LIS);
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}
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MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
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}
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void GCNUpwardRPTracker::reset(const MachineInstr &MI,
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const LiveRegSet *LiveRegsCopy) {
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GCNRPTracker::reset(MI, LiveRegsCopy, true);
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}
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void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
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assert(MRI && "call reset first");
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LastTrackedMI = &MI;
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if (MI.isDebugInstr())
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return;
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auto const RegUses = collectVirtualRegUses(MI, LIS, *MRI);
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// calc pressure at the MI (defs + uses)
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auto AtMIPressure = CurPressure;
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for (const auto &U : RegUses) {
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auto LiveMask = LiveRegs[U.RegUnit];
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AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI);
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}
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// update max pressure
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MaxPressure = max(AtMIPressure, MaxPressure);
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for (const auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual() || MO.isDead())
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continue;
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auto Reg = MO.getReg();
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auto I = LiveRegs.find(Reg);
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if (I == LiveRegs.end())
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continue;
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auto &LiveMask = I->second;
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auto PrevMask = LiveMask;
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LiveMask &= ~getDefRegMask(MO, *MRI);
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CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
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if (LiveMask.none())
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LiveRegs.erase(I);
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}
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for (const auto &U : RegUses) {
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auto &LiveMask = LiveRegs[U.RegUnit];
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auto PrevMask = LiveMask;
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LiveMask |= U.LaneMask;
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CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
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}
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assert(CurPressure == getRegPressure(*MRI, LiveRegs));
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}
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bool GCNDownwardRPTracker::reset(const MachineInstr &MI,
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const LiveRegSet *LiveRegsCopy) {
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MRI = &MI.getParent()->getParent()->getRegInfo();
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LastTrackedMI = nullptr;
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MBBEnd = MI.getParent()->end();
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NextMI = &MI;
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NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
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if (NextMI == MBBEnd)
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return false;
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GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
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return true;
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}
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bool GCNDownwardRPTracker::advanceBeforeNext() {
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assert(MRI && "call reset first");
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if (!LastTrackedMI)
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return NextMI == MBBEnd;
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assert(NextMI == MBBEnd || !NextMI->isDebugInstr());
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SlotIndex SI = NextMI == MBBEnd
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? LIS.getInstructionIndex(*LastTrackedMI).getDeadSlot()
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: LIS.getInstructionIndex(*NextMI).getBaseIndex();
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assert(SI.isValid());
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// Remove dead registers or mask bits.
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SmallSet<Register, 8> SeenRegs;
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for (auto &MO : LastTrackedMI->operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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if (MO.isUse() && !MO.readsReg())
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continue;
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if (!SeenRegs.insert(MO.getReg()).second)
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continue;
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const LiveInterval &LI = LIS.getInterval(MO.getReg());
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if (LI.hasSubRanges()) {
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auto It = LiveRegs.end();
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for (const auto &S : LI.subranges()) {
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if (!S.liveAt(SI)) {
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if (It == LiveRegs.end()) {
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It = LiveRegs.find(MO.getReg());
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if (It == LiveRegs.end())
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llvm_unreachable("register isn't live");
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}
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auto PrevMask = It->second;
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It->second &= ~S.LaneMask;
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CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
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}
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}
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if (It != LiveRegs.end() && It->second.none())
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LiveRegs.erase(It);
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} else if (!LI.liveAt(SI)) {
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auto It = LiveRegs.find(MO.getReg());
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if (It == LiveRegs.end())
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llvm_unreachable("register isn't live");
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CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
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LiveRegs.erase(It);
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}
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}
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MaxPressure = max(MaxPressure, CurPressure);
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LastTrackedMI = nullptr;
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return NextMI == MBBEnd;
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}
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void GCNDownwardRPTracker::advanceToNext() {
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LastTrackedMI = &*NextMI++;
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NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
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// Add new registers or mask bits.
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for (const auto &MO : LastTrackedMI->operands()) {
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if (!MO.isReg() || !MO.isDef())
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continue;
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Register Reg = MO.getReg();
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if (!Reg.isVirtual())
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continue;
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auto &LiveMask = LiveRegs[Reg];
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auto PrevMask = LiveMask;
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LiveMask |= getDefRegMask(MO, *MRI);
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CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
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}
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MaxPressure = max(MaxPressure, CurPressure);
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}
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bool GCNDownwardRPTracker::advance() {
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if (NextMI == MBBEnd)
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return false;
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advanceBeforeNext();
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advanceToNext();
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return true;
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}
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bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator End) {
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while (NextMI != End)
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if (!advance()) return false;
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return true;
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}
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bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator Begin,
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MachineBasicBlock::const_iterator End,
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const LiveRegSet *LiveRegsCopy) {
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reset(*Begin, LiveRegsCopy);
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return advance(End);
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}
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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LLVM_DUMP_METHOD
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Printable llvm::reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
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const GCNRPTracker::LiveRegSet &TrackedLR,
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const TargetRegisterInfo *TRI) {
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return Printable([&LISLR, &TrackedLR, TRI](raw_ostream &OS) {
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for (auto const &P : TrackedLR) {
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auto I = LISLR.find(P.first);
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if (I == LISLR.end()) {
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OS << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
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<< " isn't found in LIS reported set\n";
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} else if (I->second != P.second) {
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OS << " " << printReg(P.first, TRI)
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<< " masks doesn't match: LIS reported " << PrintLaneMask(I->second)
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<< ", tracked " << PrintLaneMask(P.second) << '\n';
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}
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}
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for (auto const &P : LISLR) {
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auto I = TrackedLR.find(P.first);
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if (I == TrackedLR.end()) {
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OS << " " << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
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<< " isn't found in tracked set\n";
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}
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}
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});
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}
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bool GCNUpwardRPTracker::isValid() const {
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const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
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const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
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const auto &TrackedLR = LiveRegs;
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if (!isEqual(LISLR, TrackedLR)) {
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dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
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" LIS reported livesets mismatch:\n"
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<< print(LISLR, *MRI);
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reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
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return false;
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}
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auto LISPressure = getRegPressure(*MRI, LISLR);
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if (LISPressure != CurPressure) {
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dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
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<< print(CurPressure) << "LIS rpt: " << print(LISPressure);
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return false;
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}
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return true;
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}
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LLVM_DUMP_METHOD
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Printable llvm::print(const GCNRPTracker::LiveRegSet &LiveRegs,
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const MachineRegisterInfo &MRI) {
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return Printable([&LiveRegs, &MRI](raw_ostream &OS) {
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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|
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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|
Register Reg = Register::index2VirtReg(I);
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|
auto It = LiveRegs.find(Reg);
|
|
if (It != LiveRegs.end() && It->second.any())
|
|
OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
|
|
<< PrintLaneMask(It->second);
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|
}
|
|
OS << '\n';
|
|
});
|
|
}
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|
|
|
LLVM_DUMP_METHOD
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|
void GCNRegPressure::dump() const { dbgs() << print(*this); }
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|
|
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#endif
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