d1af09ad96
We form VOPD instructions in the GCNCreateVOPD pass by combining back-to-back component instructions. There are strict register constraints for creating a legal VOPD, namely that the matching operands (e.g. src0x and src0y, src1x and src1y) must be in different register banks. We add a PostRA scheduler mutation to put possible VOPD components back-to-back. Depends on D128442, D128270 Reviewed By: #amdgpu, rampitec Differential Revision: https://reviews.llvm.org/D128656
33 lines
1.1 KiB
C++
33 lines
1.1 KiB
C++
//===- GCNVOPDUtils.h - GCN VOPD Utils ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the AMDGPU DAG scheduling
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/// mutation to pair VOPD instructions back to back. It also contains
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// subroutines useful in the creation of VOPD instructions
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H
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#define LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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class SIInstrInfo;
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bool checkVOPDRegConstraints(const SIInstrInfo &TII,
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const MachineInstr &FirstMI,
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const MachineInstr &SecondMI);
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std::unique_ptr<ScheduleDAGMutation> createVOPDPairingMutation();
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_VOPDUTILS_H
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