fc83f1de5d
PAL Metadata 3.0 introduces an explicit structure in metadata for the programmable registers written out by the compiler backend. Rather than using opaque registers which can change between different architectures and requires encoding the bitfield information in the backend, which may change between versions. This is the initial minimal implementation that enables the use of PAL Metadata 3.0. The change itself should be NFC for non-PAL, although the way RSRC2 register is handled has been changed slightly. The test is fairly minimal, but checks that the metadata format looks as expected and verifies a couple of special cases such as tgid_[xyz]_en handling and PsInputAddr/Ena which also change to explicit fields. Differential Revision: https://reviews.llvm.org/D147143
77 lines
2.6 KiB
C++
77 lines
2.6 KiB
C++
//===-- SIProgramInfo.cpp ----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// The SIProgramInfo tracks resource usage and hardware flags for kernels and
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/// entry functions.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "SIProgramInfo.h"
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#include "SIDefines.h"
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#include "Utils/AMDGPUBaseInfo.h"
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using namespace llvm;
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uint64_t SIProgramInfo::getComputePGMRSrc1() const {
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return S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
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S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
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S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) |
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S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode) |
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S_00B848_WGP_MODE(WgpMode) | S_00B848_MEM_ORDERED(MemOrdered);
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}
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uint64_t SIProgramInfo::getPGMRSrc1(CallingConv::ID CC) const {
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if (AMDGPU::isCompute(CC)) {
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return getComputePGMRSrc1();
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}
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uint64_t Reg = S_00B848_VGPRS(VGPRBlocks) | S_00B848_SGPRS(SGPRBlocks) |
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S_00B848_PRIORITY(Priority) | S_00B848_FLOAT_MODE(FloatMode) |
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S_00B848_PRIV(Priv) | S_00B848_DX10_CLAMP(DX10Clamp) |
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S_00B848_DEBUG_MODE(DebugMode) | S_00B848_IEEE_MODE(IEEEMode);
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switch (CC) {
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case CallingConv::AMDGPU_PS:
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Reg |= S_00B028_MEM_ORDERED(MemOrdered);
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break;
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case CallingConv::AMDGPU_VS:
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Reg |= S_00B128_MEM_ORDERED(MemOrdered);
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break;
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case CallingConv::AMDGPU_GS:
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Reg |= S_00B228_WGP_MODE(WgpMode) | S_00B228_MEM_ORDERED(MemOrdered);
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break;
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case CallingConv::AMDGPU_HS:
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Reg |= S_00B428_WGP_MODE(WgpMode) | S_00B428_MEM_ORDERED(MemOrdered);
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break;
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default:
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break;
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}
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return Reg;
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}
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uint64_t SIProgramInfo::getComputePGMRSrc2() const {
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uint64_t Reg =
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S_00B84C_SCRATCH_EN(ScratchEnable) | S_00B84C_USER_SGPR(UserSGPR) |
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S_00B84C_TRAP_HANDLER(TrapHandlerEnable) |
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S_00B84C_TGID_X_EN(TGIdXEnable) | S_00B84C_TGID_Y_EN(TGIdYEnable) |
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S_00B84C_TGID_Z_EN(TGIdZEnable) | S_00B84C_TG_SIZE_EN(TGSizeEnable) |
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S_00B84C_TIDIG_COMP_CNT(TIdIGCompCount) |
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S_00B84C_EXCP_EN_MSB(EXCPEnMSB) | S_00B84C_LDS_SIZE(LdsSize) |
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S_00B84C_EXCP_EN(EXCPEnable);
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return Reg;
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}
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uint64_t SIProgramInfo::getPGMRSrc2(CallingConv::ID CC) const {
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if (AMDGPU::isCompute(CC))
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return getComputePGMRSrc2();
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return 0;
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}
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