fc83f1de5d
PAL Metadata 3.0 introduces an explicit structure in metadata for the programmable registers written out by the compiler backend. Rather than using opaque registers which can change between different architectures and requires encoding the bitfield information in the backend, which may change between versions. This is the initial minimal implementation that enables the use of PAL Metadata 3.0. The change itself should be NFC for non-PAL, although the way RSRC2 register is handled has been changed slightly. The test is fairly minimal, but checks that the metadata format looks as expected and verifies a couple of special cases such as tgid_[xyz]_en handling and PsInputAddr/Ena which also change to explicit fields. Differential Revision: https://reviews.llvm.org/D147143
99 lines
2.9 KiB
C++
99 lines
2.9 KiB
C++
//===--- SIProgramInfo.h ----------------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Defines struct to track resource usage and hardware flags for kernels and
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/// entry functions.
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///
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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#include "llvm/IR/CallingConv.h"
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#include <cstdint>
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namespace llvm {
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/// Track resource usage for kernels / entry functions.
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struct SIProgramInfo {
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// Fields set in PGM_RSRC1 pm4 packet.
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uint32_t VGPRBlocks = 0;
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uint32_t SGPRBlocks = 0;
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uint32_t Priority = 0;
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uint32_t FloatMode = 0;
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uint32_t Priv = 0;
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uint32_t DX10Clamp = 0;
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uint32_t DebugMode = 0;
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uint32_t IEEEMode = 0;
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uint32_t WgpMode = 0; // GFX10+
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uint32_t MemOrdered = 0; // GFX10+
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uint64_t ScratchSize = 0;
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// State used to calculate fields set in PGM_RSRC2 pm4 packet.
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uint32_t LDSBlocks = 0;
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uint32_t ScratchBlocks = 0;
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// Fields set in PGM_RSRC2 pm4 packet
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uint32_t ScratchEnable = 0;
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uint32_t UserSGPR = 0;
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uint32_t TrapHandlerEnable = 0;
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uint32_t TGIdXEnable = 0;
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uint32_t TGIdYEnable = 0;
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uint32_t TGIdZEnable = 0;
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uint32_t TGSizeEnable = 0;
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uint32_t TIdIGCompCount = 0;
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uint32_t EXCPEnMSB = 0;
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uint32_t LdsSize = 0;
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uint32_t EXCPEnable = 0;
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uint64_t ComputePGMRSrc3GFX90A = 0;
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uint32_t NumVGPR = 0;
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uint32_t NumArchVGPR = 0;
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uint32_t NumAccVGPR = 0;
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uint32_t AccumOffset = 0;
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uint32_t TgSplit = 0;
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uint32_t NumSGPR = 0;
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unsigned SGPRSpill = 0;
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unsigned VGPRSpill = 0;
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uint32_t LDSSize = 0;
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bool FlatUsed = false;
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// Number of SGPRs that meets number of waves per execution unit request.
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uint32_t NumSGPRsForWavesPerEU = 0;
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// Number of VGPRs that meets number of waves per execution unit request.
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uint32_t NumVGPRsForWavesPerEU = 0;
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// Final occupancy.
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uint32_t Occupancy = 0;
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// Whether there is recursion, dynamic allocas, indirect calls or some other
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// reason there may be statically unknown stack usage.
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bool DynamicCallStack = false;
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// Bonus information for debugging.
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bool VCCUsed = false;
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SIProgramInfo() = default;
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/// Compute the value of the ComputePGMRsrc1 register.
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uint64_t getComputePGMRSrc1() const;
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uint64_t getPGMRSrc1(CallingConv::ID CC) const;
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/// Compute the value of the ComputePGMRsrc2 register.
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uint64_t getComputePGMRSrc2() const;
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uint64_t getPGMRSrc2(CallingConv::ID CC) const;
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_AMDGPU_SIPROGRAMINFO_H
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