19a004b468
Follow up to the series: 1. https://reviews.llvm.org/D140161 2. https://reviews.llvm.org/D140349 3. https://reviews.llvm.org/D140331 4. https://reviews.llvm.org/D140323 Completes the work from the previous two for remaining targets. This creates the following named passes that can be run via `llc -{start|stop}-{before|after}`: - arc-isel - arm-isel - avr-isel - bpf-isel - csky-isel - hexagon-isel - lanai-isel - loongarch-isel - m68k-isel - msp430-isel - mips-isel - nvptx-isel - ppc-codegen - riscv-isel - sparc-isel - systemz-isel - ve-isel - wasm-isel - xcore-isel A nice way to write tests for SelectionDAGISel might be to use a RUN: line like: llc -mtriple=<triple> -start-before=<arch>-isel -stop-after=finalize-isel -o - Fixes: https://github.com/llvm/llvm-project/issues/59538 Reviewed By: asb, zixuan-wu Differential Revision: https://reviews.llvm.org/D140364
100 lines
3.4 KiB
C++
100 lines
3.4 KiB
C++
//===- ARCTargetMachine.cpp - Define TargetMachine for ARC ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "ARCTargetMachine.h"
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#include "ARC.h"
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#include "ARCMachineFunctionInfo.h"
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#include "ARCTargetTransformInfo.h"
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#include "TargetInfo/ARCTargetInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/MC/TargetRegistry.h"
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#include <optional>
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using namespace llvm;
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static Reloc::Model getRelocModel(std::optional<Reloc::Model> RM) {
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return RM.value_or(Reloc::Static);
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}
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/// ARCTargetMachine ctor - Create an ILP32 architecture model
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ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM,
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CodeGenOpt::Level OL, bool JIT)
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: LLVMTargetMachine(T,
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"e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-"
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"f32:32:32-i64:32-f64:32-a:0:32-n32",
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TT, CPU, FS, Options, getRelocModel(RM),
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getEffectiveCodeModel(CM, CodeModel::Small), OL),
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TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
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Subtarget(TT, std::string(CPU), std::string(FS), *this) {
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initAsmInfo();
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}
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ARCTargetMachine::~ARCTargetMachine() = default;
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namespace {
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/// ARC Code Generator Pass Configuration Options.
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class ARCPassConfig : public TargetPassConfig {
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public:
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ARCPassConfig(ARCTargetMachine &TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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ARCTargetMachine &getARCTargetMachine() const {
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return getTM<ARCTargetMachine>();
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}
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bool addInstSelector() override;
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void addPreEmitPass() override;
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void addPreRegAlloc() override;
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};
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} // end anonymous namespace
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TargetPassConfig *ARCTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new ARCPassConfig(*this, PM);
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}
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bool ARCPassConfig::addInstSelector() {
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addPass(createARCISelDag(getARCTargetMachine(), getOptLevel()));
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return false;
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}
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void ARCPassConfig::addPreEmitPass() { addPass(createARCBranchFinalizePass()); }
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void ARCPassConfig::addPreRegAlloc() {
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addPass(createARCExpandPseudosPass());
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addPass(createARCOptAddrMode());
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}
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MachineFunctionInfo *ARCTargetMachine::createMachineFunctionInfo(
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BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const {
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return ARCFunctionInfo::create<ARCFunctionInfo>(Allocator, F, STI);
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}
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// Force static initialization.
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
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RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget());
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PassRegistry &PR = *PassRegistry::getPassRegistry();
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initializeARCDAGToDAGISelPass(PR);
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}
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TargetTransformInfo
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ARCTargetMachine::getTargetTransformInfo(const Function &F) const {
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return TargetTransformInfo(ARCTTIImpl(this, F));
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}
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