70a5c52534
Currently the a AAPCS compliant frame record is not always created for functions when it should. Although a consistent frame record might not be required in some cases, there are still scenarios where applications may want to make use of the call hierarchy made available trough it. In order to enable the use of AAPCS compliant frame records whilst keep backwards compatibility, this patch introduces a new command-line option (`-mframe-chain=[none|aapcs|aapcs+leaf]`) for Aarch32 and Thumb backends. The option allows users to explicitly select when to use it, and is also useful to ensure the extra overhead introduced by the frame records is only introduced when necessary, in particular for Thumb targets. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D125094
102 lines
4.1 KiB
C++
102 lines
4.1 KiB
C++
//===- ARMTargetFrameLowering.h - Define frame lowering for ARM -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#define LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/Support/TypeSize.h"
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namespace llvm {
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class ARMSubtarget;
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class CalleeSavedInfo;
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class MachineFunction;
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class ARMFrameLowering : public TargetFrameLowering {
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protected:
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const ARMSubtarget &STI;
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public:
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explicit ARMFrameLowering(const ARMSubtarget &sti);
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool keepFramePointer(const MachineFunction &MF) const override;
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bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
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bool hasFP(const MachineFunction &MF) const override;
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bool isFPReserved(const MachineFunction &MF) const;
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bool hasReservedCallFrame(const MachineFunction &MF) const override;
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bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
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StackOffset getFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg) const override;
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int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
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Register &FrameReg, int SPAdj) const;
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void getCalleeSaves(const MachineFunction &MF,
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BitVector &SavedRegs) const override;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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void adjustForSegmentedStacks(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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/// Returns true if the target will correctly handle shrink wrapping.
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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bool isProfitableForNoCSROpt(const Function &F) const override {
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// The no-CSR optimisation is bad for code size on ARM, because we can save
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// many registers with a single PUSH/POP pair.
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return false;
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}
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bool
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assignCalleeSavedSpillSlots(MachineFunction &MF,
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const TargetRegisterInfo *TRI,
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std::vector<CalleeSavedInfo> &CSI) const override;
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const SpillSlot *
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getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
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private:
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI, unsigned StmOpc,
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unsigned StrOpc, bool NoGap, bool (*Func)(unsigned, bool),
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unsigned NumAlignedDPRCS2Regs, unsigned MIFlags = 0) const;
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void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI, unsigned LdmOpc,
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unsigned LdrOpc, bool isVarArg, bool NoGap,
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bool (*Func)(unsigned, bool),
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unsigned NumAlignedDPRCS2Regs) const;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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