b5efec4b27
With D134950, targets get notified when a virtual register is created and/or cloned. Targets can do the needful with the delegate callback. AMDGPU propagates the virtual register flags maintained in the target file itself. They are useful to identify a certain type of machine operands while inserting spill stores and reloads. Since RegAllocFast spills the physical register itself, there is no way its virtual register can be mapped back to retrieve the flags. It can be solved by passing the virtual register as an additional argument. This argument has no use when the spill interfaces are called during the greedy allocator or even the PrologEpilogInserter and can pass a null register in such cases. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D138656
620 lines
20 KiB
C++
620 lines
20 KiB
C++
//===-- CSKYInstrInfo.h - CSKY Instruction Information --------*- C++ -*---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the CSKY implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "CSKYInstrInfo.h"
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#include "CSKYConstantPoolValue.h"
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#include "CSKYMachineFunctionInfo.h"
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#include "CSKYTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/MC/MCContext.h"
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#define DEBUG_TYPE "csky-instr-info"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "CSKYGenInstrInfo.inc"
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CSKYInstrInfo::CSKYInstrInfo(CSKYSubtarget &STI)
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: CSKYGenInstrInfo(CSKY::ADJCALLSTACKDOWN, CSKY::ADJCALLSTACKUP), STI(STI) {
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v2sf = STI.hasFPUv2SingleFloat();
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v2df = STI.hasFPUv2DoubleFloat();
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v3sf = STI.hasFPUv3SingleFloat();
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v3df = STI.hasFPUv3DoubleFloat();
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}
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static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
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SmallVectorImpl<MachineOperand> &Cond) {
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// Block ends with fall-through condbranch.
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assert(LastInst.getDesc().isConditionalBranch() &&
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"Unknown conditional branch");
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Target = LastInst.getOperand(1).getMBB();
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Cond.push_back(MachineOperand::CreateImm(LastInst.getOpcode()));
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Cond.push_back(LastInst.getOperand(0));
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}
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bool CSKYInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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TBB = FBB = nullptr;
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Cond.clear();
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end() || !isUnpredicatedTerminator(*I))
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return false;
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// Count the number of terminators and find the first unconditional or
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// indirect branch.
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MachineBasicBlock::iterator FirstUncondOrIndirectBr = MBB.end();
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int NumTerminators = 0;
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for (auto J = I.getReverse(); J != MBB.rend() && isUnpredicatedTerminator(*J);
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J++) {
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NumTerminators++;
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if (J->getDesc().isUnconditionalBranch() ||
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J->getDesc().isIndirectBranch()) {
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FirstUncondOrIndirectBr = J.getReverse();
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}
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}
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// If AllowModify is true, we can erase any terminators after
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// FirstUncondOrIndirectBR.
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if (AllowModify && FirstUncondOrIndirectBr != MBB.end()) {
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while (std::next(FirstUncondOrIndirectBr) != MBB.end()) {
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std::next(FirstUncondOrIndirectBr)->eraseFromParent();
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NumTerminators--;
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}
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I = FirstUncondOrIndirectBr;
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}
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// We can't handle blocks that end in an indirect branch.
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if (I->getDesc().isIndirectBranch())
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return true;
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// We can't handle blocks with more than 2 terminators.
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if (NumTerminators > 2)
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return true;
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// Handle a single unconditional branch.
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if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) {
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TBB = getBranchDestBlock(*I);
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return false;
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}
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// Handle a single conditional branch.
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if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) {
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parseCondBranch(*I, TBB, Cond);
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return false;
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}
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// Handle a conditional branch followed by an unconditional branch.
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if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() &&
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I->getDesc().isUnconditionalBranch()) {
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parseCondBranch(*std::prev(I), TBB, Cond);
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FBB = getBranchDestBlock(*I);
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return false;
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}
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// Otherwise, we can't handle this.
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return true;
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}
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unsigned CSKYInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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if (BytesRemoved)
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*BytesRemoved = 0;
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MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
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if (I == MBB.end())
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return 0;
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if (!I->getDesc().isUnconditionalBranch() &&
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!I->getDesc().isConditionalBranch())
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return 0;
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// Remove the branch.
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if (BytesRemoved)
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*BytesRemoved += getInstSizeInBytes(*I);
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin())
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return 1;
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--I;
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if (!I->getDesc().isConditionalBranch())
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return 1;
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// Remove the branch.
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if (BytesRemoved)
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*BytesRemoved += getInstSizeInBytes(*I);
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I->eraseFromParent();
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return 2;
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}
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MachineBasicBlock *
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CSKYInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
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assert(MI.getDesc().isBranch() && "Unexpected opcode!");
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// The branch target is always the last operand.
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int NumOp = MI.getNumExplicitOperands();
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assert(MI.getOperand(NumOp - 1).isMBB() && "Expected MBB!");
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return MI.getOperand(NumOp - 1).getMBB();
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}
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unsigned CSKYInstrInfo::insertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond, const DebugLoc &DL, int *BytesAdded) const {
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if (BytesAdded)
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*BytesAdded = 0;
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// Shouldn't be a fall through.
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assert(TBB && "insertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 2 || Cond.size() == 0) &&
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"CSKY branch conditions have two components!");
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// Unconditional branch.
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if (Cond.empty()) {
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MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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return 1;
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}
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// Either a one or two-way conditional branch.
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unsigned Opc = Cond[0].getImm();
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MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(CondMI);
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// One-way conditional branch.
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if (!FBB)
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return 1;
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// Two-way conditional branch.
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MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB);
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if (BytesAdded)
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*BytesAdded += getInstSizeInBytes(MI);
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return 2;
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}
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static unsigned getOppositeBranchOpc(unsigned Opcode) {
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switch (Opcode) {
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default:
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llvm_unreachable("Unknown conditional branch!");
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case CSKY::BT32:
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return CSKY::BF32;
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case CSKY::BT16:
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return CSKY::BF16;
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case CSKY::BF32:
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return CSKY::BT32;
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case CSKY::BF16:
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return CSKY::BT16;
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case CSKY::BHZ32:
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return CSKY::BLSZ32;
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case CSKY::BHSZ32:
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return CSKY::BLZ32;
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case CSKY::BLZ32:
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return CSKY::BHSZ32;
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case CSKY::BLSZ32:
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return CSKY::BHZ32;
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case CSKY::BNEZ32:
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return CSKY::BEZ32;
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case CSKY::BEZ32:
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return CSKY::BNEZ32;
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}
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}
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bool CSKYInstrInfo::reverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Cond) const {
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assert((Cond.size() == 2) && "Invalid branch condition!");
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Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));
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return false;
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}
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Register CSKYInstrInfo::movImm(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, uint64_t Val,
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MachineInstr::MIFlag Flag) const {
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if (!isInt<32>(Val))
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report_fatal_error("Should only materialize 32-bit constants.");
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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Register DstReg;
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if (STI.hasE2()) {
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DstReg = MRI.createVirtualRegister(&CSKY::GPRRegClass);
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if (isUInt<16>(Val)) {
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BuildMI(MBB, MBBI, DL, get(CSKY::MOVI32), DstReg)
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.addImm(Val & 0xFFFF)
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.setMIFlags(Flag);
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} else if (isShiftedUInt<16, 16>(Val)) {
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BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg)
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.addImm((Val >> 16) & 0xFFFF)
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.setMIFlags(Flag);
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} else {
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BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg)
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.addImm((Val >> 16) & 0xFFFF)
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.setMIFlags(Flag);
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BuildMI(MBB, MBBI, DL, get(CSKY::ORI32), DstReg)
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.addReg(DstReg)
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.addImm(Val & 0xFFFF)
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.setMIFlags(Flag);
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}
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} else {
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DstReg = MRI.createVirtualRegister(&CSKY::mGPRRegClass);
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if (isUInt<8>(Val)) {
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BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg)
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.addImm(Val & 0xFF)
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.setMIFlags(Flag);
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} else if (isUInt<16>(Val)) {
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BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg)
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.addImm((Val >> 8) & 0xFF)
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.setMIFlags(Flag);
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BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg)
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.addReg(DstReg)
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.addImm(8)
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.setMIFlags(Flag);
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if ((Val & 0xFF) != 0)
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BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg)
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.addReg(DstReg)
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.addImm(Val & 0xFF)
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.setMIFlags(Flag);
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} else if (isUInt<24>(Val)) {
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BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg)
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.addImm((Val >> 16) & 0xFF)
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.setMIFlags(Flag);
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BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg)
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.addReg(DstReg)
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.addImm(8)
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.setMIFlags(Flag);
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if (((Val >> 8) & 0xFF) != 0)
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BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg)
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.addReg(DstReg)
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.addImm((Val >> 8) & 0xFF)
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.setMIFlags(Flag);
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BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg)
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.addReg(DstReg)
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.addImm(8)
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.setMIFlags(Flag);
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if ((Val & 0xFF) != 0)
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BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg)
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.addReg(DstReg)
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.addImm(Val & 0xFF)
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.setMIFlags(Flag);
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} else {
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BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg)
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.addImm((Val >> 24) & 0xFF)
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.setMIFlags(Flag);
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BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg)
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.addReg(DstReg)
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.addImm(8)
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.setMIFlags(Flag);
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if (((Val >> 16) & 0xFF) != 0)
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BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg)
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.addReg(DstReg)
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.addImm((Val >> 16) & 0xFF)
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.setMIFlags(Flag);
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BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg)
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.addReg(DstReg)
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.addImm(8)
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.setMIFlags(Flag);
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if (((Val >> 8) & 0xFF) != 0)
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BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg)
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.addReg(DstReg)
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.addImm((Val >> 8) & 0xFF)
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.setMIFlags(Flag);
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BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg)
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.addReg(DstReg)
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.addImm(8)
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.setMIFlags(Flag);
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if ((Val & 0xFF) != 0)
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BuildMI(MBB, MBBI, DL, get(CSKY::ADDI16), DstReg)
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.addReg(DstReg)
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.addImm(Val & 0xFF)
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.setMIFlags(Flag);
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}
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}
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return DstReg;
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}
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unsigned CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case CSKY::LD16B:
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case CSKY::LD16H:
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case CSKY::LD16W:
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case CSKY::LD32B:
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case CSKY::LD32BS:
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case CSKY::LD32H:
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case CSKY::LD32HS:
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case CSKY::LD32W:
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case CSKY::FLD_S:
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case CSKY::FLD_D:
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case CSKY::f2FLD_S:
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case CSKY::f2FLD_D:
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case CSKY::RESTORE_CARRY:
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break;
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}
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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return 0;
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}
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unsigned CSKYInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const {
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switch (MI.getOpcode()) {
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default:
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return 0;
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case CSKY::ST16B:
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case CSKY::ST16H:
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case CSKY::ST16W:
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case CSKY::ST32B:
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case CSKY::ST32H:
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case CSKY::ST32W:
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case CSKY::FST_S:
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case CSKY::FST_D:
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case CSKY::f2FST_S:
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case CSKY::f2FST_D:
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case CSKY::SPILL_CARRY:
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break;
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}
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if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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MI.getOperand(2).getImm() == 0) {
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FrameIndex = MI.getOperand(1).getIndex();
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return MI.getOperand(0).getReg();
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}
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return 0;
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}
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void CSKYInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register SrcReg, bool IsKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Opcode = 0;
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if (CSKY::GPRRegClass.hasSubClassEq(RC)) {
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Opcode = CSKY::ST32W; // Optimize for 16bit
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} else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) {
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Opcode = CSKY::SPILL_CARRY;
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CFI->setSpillsCR();
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} else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC))
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Opcode = CSKY::FST_S;
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else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC))
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Opcode = CSKY::FST_D;
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else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC))
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Opcode = CSKY::f2FST_S;
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else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC))
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Opcode = CSKY::f2FST_D;
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else {
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llvm_unreachable("Unknown RegisterClass");
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}
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
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MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
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BuildMI(MBB, I, DL, get(Opcode))
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.addReg(SrcReg, getKillRegState(IsKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO);
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}
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void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI,
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Register VReg) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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unsigned Opcode = 0;
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if (CSKY::GPRRegClass.hasSubClassEq(RC)) {
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Opcode = CSKY::LD32W;
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} else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) {
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Opcode = CSKY::RESTORE_CARRY;
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CFI->setSpillsCR();
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} else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC))
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Opcode = CSKY::FLD_S;
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else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC))
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Opcode = CSKY::FLD_D;
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else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC))
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Opcode = CSKY::f2FLD_S;
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else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC))
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Opcode = CSKY::f2FLD_D;
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|
else {
|
|
llvm_unreachable("Unknown RegisterClass");
|
|
}
|
|
|
|
MachineMemOperand *MMO = MF.getMachineMemOperand(
|
|
MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
|
|
MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
|
|
|
|
BuildMI(MBB, I, DL, get(Opcode), DestReg)
|
|
.addFrameIndex(FI)
|
|
.addImm(0)
|
|
.addMemOperand(MMO);
|
|
}
|
|
|
|
void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I,
|
|
const DebugLoc &DL, MCRegister DestReg,
|
|
MCRegister SrcReg, bool KillSrc) const {
|
|
if (CSKY::GPRRegClass.contains(SrcReg) &&
|
|
CSKY::CARRYRegClass.contains(DestReg)) {
|
|
if (STI.hasE2()) {
|
|
BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc))
|
|
.addImm(0);
|
|
} else {
|
|
assert(SrcReg < CSKY::R8);
|
|
BuildMI(MBB, I, DL, get(CSKY::BTSTI16), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc))
|
|
.addImm(0);
|
|
}
|
|
return;
|
|
}
|
|
|
|
if (CSKY::CARRYRegClass.contains(SrcReg) &&
|
|
CSKY::GPRRegClass.contains(DestReg)) {
|
|
|
|
if (STI.hasE2()) {
|
|
BuildMI(MBB, I, DL, get(CSKY::MVC32), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
} else {
|
|
assert(DestReg < CSKY::R16);
|
|
assert(DestReg < CSKY::R8);
|
|
BuildMI(MBB, I, DL, get(CSKY::MOVI16), DestReg).addImm(0);
|
|
BuildMI(MBB, I, DL, get(CSKY::ADDC16))
|
|
.addReg(DestReg, RegState::Define)
|
|
.addReg(SrcReg, RegState::Define)
|
|
.addReg(DestReg, getKillRegState(true))
|
|
.addReg(DestReg, getKillRegState(true))
|
|
.addReg(SrcReg, getKillRegState(true));
|
|
BuildMI(MBB, I, DL, get(CSKY::BTSTI16))
|
|
.addReg(SrcReg, RegState::Define | getDeadRegState(KillSrc))
|
|
.addReg(DestReg)
|
|
.addImm(0);
|
|
}
|
|
return;
|
|
}
|
|
|
|
unsigned Opcode = 0;
|
|
if (CSKY::GPRRegClass.contains(DestReg, SrcReg))
|
|
Opcode = STI.hasE2() ? CSKY::MOV32 : CSKY::MOV16;
|
|
else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg))
|
|
Opcode = CSKY::FMOV_S;
|
|
else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg))
|
|
Opcode = CSKY::f2FMOV_S;
|
|
else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg))
|
|
Opcode = CSKY::FMOV_D;
|
|
else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg))
|
|
Opcode = CSKY::f2FMOV_D;
|
|
else if (v2sf && CSKY::sFPR32RegClass.contains(SrcReg) &&
|
|
CSKY::GPRRegClass.contains(DestReg))
|
|
Opcode = CSKY::FMFVRL;
|
|
else if (v3sf && CSKY::FPR32RegClass.contains(SrcReg) &&
|
|
CSKY::GPRRegClass.contains(DestReg))
|
|
Opcode = CSKY::f2FMFVRL;
|
|
else if (v2df && CSKY::sFPR64RegClass.contains(SrcReg) &&
|
|
CSKY::GPRRegClass.contains(DestReg))
|
|
Opcode = CSKY::FMFVRL_D;
|
|
else if (v3df && CSKY::FPR64RegClass.contains(SrcReg) &&
|
|
CSKY::GPRRegClass.contains(DestReg))
|
|
Opcode = CSKY::f2FMFVRL_D;
|
|
else if (v2sf && CSKY::GPRRegClass.contains(SrcReg) &&
|
|
CSKY::sFPR32RegClass.contains(DestReg))
|
|
Opcode = CSKY::FMTVRL;
|
|
else if (v3sf && CSKY::GPRRegClass.contains(SrcReg) &&
|
|
CSKY::FPR32RegClass.contains(DestReg))
|
|
Opcode = CSKY::f2FMTVRL;
|
|
else if (v2df && CSKY::GPRRegClass.contains(SrcReg) &&
|
|
CSKY::sFPR64RegClass.contains(DestReg))
|
|
Opcode = CSKY::FMTVRL_D;
|
|
else if (v3df && CSKY::GPRRegClass.contains(SrcReg) &&
|
|
CSKY::FPR64RegClass.contains(DestReg))
|
|
Opcode = CSKY::f2FMTVRL_D;
|
|
else {
|
|
LLVM_DEBUG(dbgs() << "src = " << SrcReg << ", dst = " << DestReg);
|
|
LLVM_DEBUG(I->dump());
|
|
llvm_unreachable("Unknown RegisterClass");
|
|
}
|
|
|
|
BuildMI(MBB, I, DL, get(Opcode), DestReg)
|
|
.addReg(SrcReg, getKillRegState(KillSrc));
|
|
}
|
|
|
|
Register CSKYInstrInfo::getGlobalBaseReg(MachineFunction &MF) const {
|
|
CSKYMachineFunctionInfo *CFI = MF.getInfo<CSKYMachineFunctionInfo>();
|
|
MachineConstantPool *MCP = MF.getConstantPool();
|
|
MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
Register GlobalBaseReg = CFI->getGlobalBaseReg();
|
|
if (GlobalBaseReg != 0)
|
|
return GlobalBaseReg;
|
|
|
|
// Insert a pseudo instruction to set the GlobalBaseReg into the first
|
|
// MBB of the function
|
|
MachineBasicBlock &FirstMBB = MF.front();
|
|
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
|
DebugLoc DL;
|
|
|
|
CSKYConstantPoolValue *CPV = CSKYConstantPoolSymbol::Create(
|
|
Type::getInt32Ty(MF.getFunction().getContext()), "_GLOBAL_OFFSET_TABLE_",
|
|
0, CSKYCP::ADDR);
|
|
|
|
unsigned CPI = MCP->getConstantPoolIndex(CPV, Align(4));
|
|
|
|
MachineMemOperand *MO =
|
|
MF.getMachineMemOperand(MachinePointerInfo::getConstantPool(MF),
|
|
MachineMemOperand::MOLoad, 4, Align(4));
|
|
BuildMI(FirstMBB, MBBI, DL, get(CSKY::LRW32), CSKY::R28)
|
|
.addConstantPoolIndex(CPI)
|
|
.addMemOperand(MO);
|
|
|
|
GlobalBaseReg = MRI.createVirtualRegister(&CSKY::GPRRegClass);
|
|
BuildMI(FirstMBB, MBBI, DL, get(TargetOpcode::COPY), GlobalBaseReg)
|
|
.addReg(CSKY::R28);
|
|
|
|
CFI->setGlobalBaseReg(GlobalBaseReg);
|
|
return GlobalBaseReg;
|
|
}
|
|
|
|
unsigned CSKYInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
|
switch (MI.getOpcode()) {
|
|
default:
|
|
return MI.getDesc().getSize();
|
|
case CSKY::CONSTPOOL_ENTRY:
|
|
return MI.getOperand(2).getImm();
|
|
case CSKY::SPILL_CARRY:
|
|
case CSKY::RESTORE_CARRY:
|
|
case CSKY::PseudoTLSLA32:
|
|
return 8;
|
|
case TargetOpcode::INLINEASM_BR:
|
|
case TargetOpcode::INLINEASM: {
|
|
const MachineFunction *MF = MI.getParent()->getParent();
|
|
const char *AsmStr = MI.getOperand(0).getSymbolName();
|
|
return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
|
|
}
|
|
}
|
|
}
|