d6775052de
Support of variadic functions triggers an assertion on several tests from llvm/test/CodeGen/Generic/ if nvptx64-* is specified as a default triplet: Support for variadic functions (unsized array parameter) introduced in PTX ISA version 6.0 and requires target sm_30. That happens because those tests contain variadic function calls and default versions of both PTX ISA (3.2) and architecture (sm_20) are below the minimally required. There were no observable problems with these tests before adding support of variadic functions, because nvptx backend just didn't handle them properly generating invalid PTX code. Differential Revision: https://reviews.llvm.org/D141054
68 lines
2.1 KiB
C++
68 lines
2.1 KiB
C++
//===- NVPTXSubtarget.cpp - NVPTX Subtarget Information -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the NVPTX specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTXSubtarget.h"
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#include "NVPTXTargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "nvptx-subtarget"
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#define GET_SUBTARGETINFO_ENUM
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "NVPTXGenSubtargetInfo.inc"
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static cl::opt<bool>
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NoF16Math("nvptx-no-f16-math", cl::Hidden,
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cl::desc("NVPTX Specific: Disable generation of f16 math ops."),
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cl::init(false));
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// Pin the vtable to this file.
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void NVPTXSubtarget::anchor() {}
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NVPTXSubtarget &NVPTXSubtarget::initializeSubtargetDependencies(StringRef CPU,
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StringRef FS) {
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// Provide the default CPU if we don't have one.
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TargetName = std::string(CPU.empty() ? "sm_30" : CPU);
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ParseSubtargetFeatures(TargetName, /*TuneCPU*/ TargetName, FS);
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// Set default to PTX 6.0 (CUDA 9.0)
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if (PTXVersion == 0) {
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PTXVersion = 60;
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}
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return *this;
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}
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NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS,
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const NVPTXTargetMachine &TM)
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: NVPTXGenSubtargetInfo(TT, CPU, /*TuneCPU*/ CPU, FS), PTXVersion(0),
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SmVersion(20), TM(TM),
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TLInfo(TM, initializeSubtargetDependencies(CPU, FS)) {}
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bool NVPTXSubtarget::hasImageHandles() const {
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// Enable handles for Kepler+, where CUDA supports indirect surfaces and
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// textures
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if (TM.getDrvInterface() == NVPTX::CUDA)
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return (SmVersion >= 30);
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// Disabled, otherwise
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return false;
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}
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bool NVPTXSubtarget::allowFP16Math() const {
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return hasFP16Math() && NoF16Math == false;
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}
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