3ff319c690
According to D127731, PPCTLSDynamicCall does not preserve LiveIntervals, so stop claiming that it does and remove the code that tried to repair them. NFCI. Differential Revision: https://reviews.llvm.org/D128421
220 lines
8.0 KiB
C++
220 lines
8.0 KiB
C++
//===---------- PPCTLSDynamicCall.cpp - TLS Dynamic Call Fixup ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass expands ADDItls{ld,gd}LADDR[32] machine instructions into
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// separate ADDItls[gd]L[32] and GETtlsADDR[32] instructions, both of
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// which define GPR3. A copy is added from GPR3 to the target virtual
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// register of the original instruction. The GETtlsADDR[32] is really
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// a call instruction, so its target register is constrained to be GPR3.
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// This is not true of ADDItls[gd]L[32], but there is a legacy linker
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// optimization bug that requires the target register of the addi of
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// a local- or general-dynamic TLS access sequence to be GPR3.
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//
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// This is done in a late pass so that TLS variable accesses can be
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// fully commoned by MachineCSE.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCInstrBuilder.h"
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#include "PPCInstrInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-tls-dynamic-call"
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namespace {
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struct PPCTLSDynamicCall : public MachineFunctionPass {
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static char ID;
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PPCTLSDynamicCall() : MachineFunctionPass(ID) {
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initializePPCTLSDynamicCallPass(*PassRegistry::getPassRegistry());
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}
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const PPCInstrInfo *TII;
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protected:
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bool processBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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bool NeedFence = true;
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bool Is64Bit = MBB.getParent()->getSubtarget<PPCSubtarget>().isPPC64();
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bool IsAIX = MBB.getParent()->getSubtarget<PPCSubtarget>().isAIXABI();
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bool IsPCREL = false;
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for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end();
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I != IE;) {
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MachineInstr &MI = *I;
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IsPCREL = isPCREL(MI);
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if (MI.getOpcode() != PPC::ADDItlsgdLADDR &&
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MI.getOpcode() != PPC::ADDItlsldLADDR &&
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MI.getOpcode() != PPC::ADDItlsgdLADDR32 &&
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MI.getOpcode() != PPC::ADDItlsldLADDR32 &&
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MI.getOpcode() != PPC::TLSGDAIX &&
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MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) {
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// Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
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// as scheduling fences, we skip creating fences if we already
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// have existing ADJCALLSTACKDOWN/UP to avoid nesting,
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// which causes verification error with -verify-machineinstrs.
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if (MI.getOpcode() == PPC::ADJCALLSTACKDOWN)
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NeedFence = false;
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else if (MI.getOpcode() == PPC::ADJCALLSTACKUP)
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NeedFence = true;
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++I;
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continue;
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}
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LLVM_DEBUG(dbgs() << "TLS Dynamic Call Fixup:\n " << MI);
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Register OutReg = MI.getOperand(0).getReg();
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Register InReg = PPC::NoRegister;
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Register GPR3 = Is64Bit ? PPC::X3 : PPC::R3;
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Register GPR4 = Is64Bit ? PPC::X4 : PPC::R4;
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if (!IsPCREL)
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InReg = MI.getOperand(1).getReg();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Opc1, Opc2;
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("Opcode inconsistency error");
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case PPC::ADDItlsgdLADDR:
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Opc1 = PPC::ADDItlsgdL;
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Opc2 = PPC::GETtlsADDR;
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break;
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case PPC::ADDItlsldLADDR:
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Opc1 = PPC::ADDItlsldL;
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Opc2 = PPC::GETtlsldADDR;
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break;
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case PPC::ADDItlsgdLADDR32:
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Opc1 = PPC::ADDItlsgdL32;
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Opc2 = PPC::GETtlsADDR32;
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break;
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case PPC::ADDItlsldLADDR32:
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Opc1 = PPC::ADDItlsldL32;
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Opc2 = PPC::GETtlsldADDR32;
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break;
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case PPC::TLSGDAIX8:
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// TLSGDAIX8 is expanded to two copies and GET_TLS_ADDR, so we only
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// set Opc2 here.
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Opc2 = PPC::GETtlsADDR64AIX;
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break;
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case PPC::TLSGDAIX:
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// TLSGDAIX is expanded to two copies and GET_TLS_ADDR, so we only
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// set Opc2 here.
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Opc2 = PPC::GETtlsADDR32AIX;
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break;
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case PPC::PADDI8pc:
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assert(IsPCREL && "Expecting General/Local Dynamic PCRel");
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Opc1 = PPC::PADDI8pc;
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Opc2 = MI.getOperand(2).getTargetFlags() ==
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PPCII::MO_GOT_TLSGD_PCREL_FLAG
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? PPC::GETtlsADDRPCREL
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: PPC::GETtlsldADDRPCREL;
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}
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// We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
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// as scheduling fence to avoid it is scheduled before
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// mflr in the prologue and the address in LR is clobbered (PR25839).
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// We don't really need to save data to the stack - the clobbered
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// registers are already saved when the SDNode (e.g. PPCaddiTlsgdLAddr)
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// gets translated to the pseudo instruction (e.g. ADDItlsgdLADDR).
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if (NeedFence)
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BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0)
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.addImm(0);
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if (IsAIX) {
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// The variable offset and region handle are copied in r4 and r3. The
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// copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX.
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BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4)
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.addReg(MI.getOperand(1).getReg());
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BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3)
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.addReg(MI.getOperand(2).getReg());
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BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4);
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} else {
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MachineInstr *Addi;
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if (IsPCREL) {
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Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0);
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} else {
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// Expand into two ops built prior to the existing instruction.
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assert(InReg != PPC::NoRegister && "Operand must be a register");
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Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg);
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}
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Addi->addOperand(MI.getOperand(2));
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MachineInstr *Call =
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(BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3));
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if (IsPCREL)
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Call->addOperand(MI.getOperand(2));
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else
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Call->addOperand(MI.getOperand(3));
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}
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if (NeedFence)
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BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKUP)).addImm(0).addImm(0);
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BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
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.addReg(GPR3);
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// Move past the original instruction and remove it.
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++I;
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MI.removeFromParent();
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Changed = true;
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}
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return Changed;
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}
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public:
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bool isPCREL(const MachineInstr &MI) {
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return (MI.getOpcode() == PPC::PADDI8pc) &&
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(MI.getOperand(2).getTargetFlags() ==
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PPCII::MO_GOT_TLSGD_PCREL_FLAG ||
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MI.getOperand(2).getTargetFlags() ==
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PPCII::MO_GOT_TLSLD_PCREL_FLAG);
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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TII = MF.getSubtarget<PPCSubtarget>().getInstrInfo();
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bool Changed = false;
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for (MachineBasicBlock &B : llvm::make_early_inc_range(MF))
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if (processBlock(B))
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Changed = true;
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return Changed;
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.addRequired<SlotIndexes>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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}
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INITIALIZE_PASS_BEGIN(PPCTLSDynamicCall, DEBUG_TYPE,
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"PowerPC TLS Dynamic Call Fixup", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
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INITIALIZE_PASS_END(PPCTLSDynamicCall, DEBUG_TYPE,
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"PowerPC TLS Dynamic Call Fixup", false, false)
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char PPCTLSDynamicCall::ID = 0;
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FunctionPass*
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llvm::createPPCTLSDynamicCallPass() { return new PPCTLSDynamicCall(); }
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