96a7e05756
I only added Zicsr to CPUs that didn't already have an implication through the F extension. As far as I could tell from searching Rocket and Syntacore repositories, all the CPUs support these instructions. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D147261
185 lines
8.8 KiB
TableGen
185 lines
8.8 KiB
TableGen
//===-- RISCVProcessors.td - RISC-V Processors -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// RISC-V processors supported.
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//===----------------------------------------------------------------------===//
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class RISCVProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> f,
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list<SubtargetFeature> tunef = [],
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string default_march = "">
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: ProcessorModel<n, m, f, tunef> {
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string DefaultMarch = default_march;
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}
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class RISCVTuneProcessorModel<string n,
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SchedMachineModel m,
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list<SubtargetFeature> tunef = [],
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list<SubtargetFeature> f = []>
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: ProcessorModel<n, m, f,tunef>;
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def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
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NoSchedModel,
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[Feature32Bit]>;
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def GENERIC_RV64 : RISCVProcessorModel<"generic-rv64",
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NoSchedModel,
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[Feature64Bit]>;
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// Support generic for compatibility with other targets. The triple will be used
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// to change to the appropriate rv32/rv64 version.
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def : ProcessorModel<"generic", NoSchedModel, []>;
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def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr]>;
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def ROCKET : RISCVTuneProcessorModel<"rocket",
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RocketModel>;
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def SIFIVE_7 : RISCVTuneProcessorModel<"sifive-7-series",
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SiFive7Model,
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[TuneSiFive7]>;
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def SIFIVE_E20 : RISCVProcessorModel<"sifive-e20",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC]>;
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def SIFIVE_E21 : RISCVProcessorModel<"sifive-e21",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_E24 : RISCVProcessorModel<"sifive-e24",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def SIFIVE_E31 : RISCVProcessorModel<"sifive-e31",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtZicsr,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_E34 : RISCVProcessorModel<"sifive-e34",
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RocketModel,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC]>;
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def SIFIVE_E76 : RISCVProcessorModel<"sifive-e76",
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SiFive7Model,
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[Feature32Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtC],
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[TuneSiFive7]>;
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def SIFIVE_S21 : RISCVProcessorModel<"sifive-s21",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_S51 : RISCVProcessorModel<"sifive-s51",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtC]>;
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def SIFIVE_S54 : RISCVProcessorModel<"sifive-s54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def SIFIVE_S76 : RISCVProcessorModel<"sifive-s76",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneSiFive7]>;
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def SIFIVE_U54 : RISCVProcessorModel<"sifive-u54",
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RocketModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC]>;
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def SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
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SiFive7Model,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC],
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[TuneSiFive7]>;
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def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtC],
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[TuneNoDefaultUnroll]>;
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def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
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SyntacoreSCR1Model,
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[Feature32Bit,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtC],
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[TuneNoDefaultUnroll]>;
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