fffbfe7c0c
WebAssemblyUtils depends on CodeGen which depends on all middle end optimization libraries. This component is used by WebAssembly's AsmParser, Disassembler, and MCTargetDesc libraries. Because of this, any MC layer tool built with WebAssembly support includes a larger portion of LLVM than it should. To fix this I've created an MC only version of WebAssemblyTypeUtilities.cpp in MCTargetDesc to be used by the MC components. This shrinks llvm-objdump and llvm-mc on my local release+asserts build by 5-6 MB. Reviewed By: MaskRay, aheejin Differential Revision: https://reviews.llvm.org/D144354
368 lines
13 KiB
C++
368 lines
13 KiB
C++
//=- WebAssemblyInstPrinter.cpp - WebAssembly assembly instruction printing -=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// Print MCInst instructions to wasm format.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/WebAssemblyInstPrinter.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "MCTargetDesc/WebAssemblyMCTypeUtilities.h"
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#include "WebAssembly.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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#include "WebAssemblyGenAsmWriter.inc"
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WebAssemblyInstPrinter::WebAssemblyInstPrinter(const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI)
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: MCInstPrinter(MAI, MII, MRI) {}
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void WebAssemblyInstPrinter::printRegName(raw_ostream &OS,
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MCRegister Reg) const {
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assert(Reg.id() != WebAssemblyFunctionInfo::UnusedReg);
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// Note that there's an implicit local.get/local.set here!
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OS << "$" << Reg.id();
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}
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void WebAssemblyInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot,
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const MCSubtargetInfo &STI,
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raw_ostream &OS) {
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switch (MI->getOpcode()) {
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case WebAssembly::CALL_INDIRECT_S:
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case WebAssembly::RET_CALL_INDIRECT_S: {
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// A special case for call_indirect (and ret_call_indirect), if the table
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// operand is a symbol: the order of the type and table operands is inverted
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// in the text format relative to the binary format. Otherwise if table the
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// operand isn't a symbol, then we have an MVP compilation unit, and the
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// table shouldn't appear in the output.
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OS << "\t";
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OS << getMnemonic(MI).first;
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OS << " ";
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assert(MI->getNumOperands() == 2);
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const unsigned TypeOperand = 0;
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const unsigned TableOperand = 1;
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if (MI->getOperand(TableOperand).isExpr()) {
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printOperand(MI, TableOperand, OS);
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OS << ", ";
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} else {
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assert(MI->getOperand(TableOperand).getImm() == 0);
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}
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printOperand(MI, TypeOperand, OS);
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break;
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}
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default:
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// Print the instruction (this uses the AsmStrings from the .td files).
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printInstruction(MI, Address, OS);
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break;
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}
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// Print any additional variadic operands.
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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if (Desc.isVariadic()) {
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if ((Desc.getNumOperands() == 0 && MI->getNumOperands() > 0) ||
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Desc.variadicOpsAreDefs())
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OS << "\t";
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unsigned Start = Desc.getNumOperands();
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unsigned NumVariadicDefs = 0;
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if (Desc.variadicOpsAreDefs()) {
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// The number of variadic defs is encoded in an immediate by MCInstLower
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NumVariadicDefs = MI->getOperand(0).getImm();
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Start = 1;
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}
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bool NeedsComma = Desc.getNumOperands() > 0 && !Desc.variadicOpsAreDefs();
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for (auto I = Start, E = MI->getNumOperands(); I < E; ++I) {
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if (MI->getOpcode() == WebAssembly::CALL_INDIRECT &&
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I - Start == NumVariadicDefs) {
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// Skip type and table arguments when printing for tests.
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++I;
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continue;
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}
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if (NeedsComma)
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OS << ", ";
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printOperand(MI, I, OS, I - Start < NumVariadicDefs);
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NeedsComma = true;
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}
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}
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// Print any added annotation.
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printAnnotation(OS, Annot);
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if (CommentStream) {
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// Observe any effects on the control flow stack, for use in annotating
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// control flow label references.
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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default:
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break;
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case WebAssembly::LOOP:
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case WebAssembly::LOOP_S:
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printAnnotation(OS, "label" + utostr(ControlFlowCounter) + ':');
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ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, true));
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return;
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case WebAssembly::BLOCK:
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case WebAssembly::BLOCK_S:
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ControlFlowStack.push_back(std::make_pair(ControlFlowCounter++, false));
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return;
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case WebAssembly::TRY:
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case WebAssembly::TRY_S:
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ControlFlowStack.push_back(std::make_pair(ControlFlowCounter, false));
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TryStack.push_back(ControlFlowCounter++);
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EHInstStack.push_back(TRY);
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return;
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case WebAssembly::END_LOOP:
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case WebAssembly::END_LOOP_S:
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if (ControlFlowStack.empty()) {
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printAnnotation(OS, "End marker mismatch!");
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} else {
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ControlFlowStack.pop_back();
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}
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return;
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case WebAssembly::END_BLOCK:
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case WebAssembly::END_BLOCK_S:
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if (ControlFlowStack.empty()) {
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printAnnotation(OS, "End marker mismatch!");
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} else {
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printAnnotation(
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OS, "label" + utostr(ControlFlowStack.pop_back_val().first) + ':');
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}
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return;
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case WebAssembly::END_TRY:
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case WebAssembly::END_TRY_S:
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if (ControlFlowStack.empty() || EHInstStack.empty()) {
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printAnnotation(OS, "End marker mismatch!");
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} else {
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printAnnotation(
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OS, "label" + utostr(ControlFlowStack.pop_back_val().first) + ':');
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EHInstStack.pop_back();
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}
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return;
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case WebAssembly::CATCH:
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case WebAssembly::CATCH_S:
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case WebAssembly::CATCH_ALL:
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case WebAssembly::CATCH_ALL_S:
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// There can be multiple catch instructions for one try instruction, so
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// we print a label only for the first 'catch' label.
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if (EHInstStack.empty()) {
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printAnnotation(OS, "try-catch mismatch!");
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} else if (EHInstStack.back() == CATCH_ALL) {
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printAnnotation(OS, "catch/catch_all cannot occur after catch_all");
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} else if (EHInstStack.back() == TRY) {
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if (TryStack.empty()) {
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printAnnotation(OS, "try-catch mismatch!");
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} else {
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printAnnotation(OS, "catch" + utostr(TryStack.pop_back_val()) + ':');
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}
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EHInstStack.pop_back();
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if (Opc == WebAssembly::CATCH || Opc == WebAssembly::CATCH_S) {
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EHInstStack.push_back(CATCH);
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} else {
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EHInstStack.push_back(CATCH_ALL);
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}
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}
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return;
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case WebAssembly::RETHROW:
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case WebAssembly::RETHROW_S:
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// 'rethrow' rethrows to the nearest enclosing catch scope, if any. If
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// there's no enclosing catch scope, it throws up to the caller.
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if (TryStack.empty()) {
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printAnnotation(OS, "to caller");
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} else {
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printAnnotation(OS, "down to catch" + utostr(TryStack.back()));
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}
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return;
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case WebAssembly::DELEGATE:
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case WebAssembly::DELEGATE_S:
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if (ControlFlowStack.empty() || TryStack.empty() || EHInstStack.empty()) {
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printAnnotation(OS, "try-delegate mismatch!");
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} else {
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// 'delegate' is
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// 1. A marker for the end of block label
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// 2. A destination for throwing instructions
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// 3. An instruction that itself rethrows to another 'catch'
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assert(ControlFlowStack.back().first == TryStack.back());
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std::string Label = "label/catch" +
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utostr(ControlFlowStack.pop_back_val().first) +
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": ";
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TryStack.pop_back();
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EHInstStack.pop_back();
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uint64_t Depth = MI->getOperand(0).getImm();
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if (Depth >= ControlFlowStack.size()) {
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Label += "to caller";
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} else {
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const auto &Pair = ControlFlowStack.rbegin()[Depth];
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if (Pair.second)
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printAnnotation(OS, "delegate cannot target a loop");
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else
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Label += "down to catch" + utostr(Pair.first);
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}
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printAnnotation(OS, Label);
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}
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return;
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}
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// Annotate any control flow label references.
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unsigned NumFixedOperands = Desc.NumOperands;
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SmallSet<uint64_t, 8> Printed;
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for (unsigned I = 0, E = MI->getNumOperands(); I < E; ++I) {
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// See if this operand denotes a basic block target.
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if (I < NumFixedOperands) {
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// A non-variable_ops operand, check its type.
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if (Desc.operands()[I].OperandType != WebAssembly::OPERAND_BASIC_BLOCK)
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continue;
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} else {
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// A variable_ops operand, which currently can be immediates (used in
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// br_table) which are basic block targets, or for call instructions
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// when using -wasm-keep-registers (in which case they are registers,
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// and should not be processed).
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if (!MI->getOperand(I).isImm())
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continue;
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}
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uint64_t Depth = MI->getOperand(I).getImm();
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if (!Printed.insert(Depth).second)
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continue;
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if (Depth >= ControlFlowStack.size()) {
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printAnnotation(OS, "Invalid depth argument!");
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} else {
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const auto &Pair = ControlFlowStack.rbegin()[Depth];
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printAnnotation(OS, utostr(Depth) + ": " +
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(Pair.second ? "up" : "down") + " to label" +
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utostr(Pair.first));
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}
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}
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}
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}
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static std::string toString(const APFloat &FP) {
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// Print NaNs with custom payloads specially.
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if (FP.isNaN() && !FP.bitwiseIsEqual(APFloat::getQNaN(FP.getSemantics())) &&
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!FP.bitwiseIsEqual(
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APFloat::getQNaN(FP.getSemantics(), /*Negative=*/true))) {
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APInt AI = FP.bitcastToAPInt();
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return std::string(AI.isNegative() ? "-" : "") + "nan:0x" +
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utohexstr(AI.getZExtValue() &
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(AI.getBitWidth() == 32 ? INT64_C(0x007fffff)
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: INT64_C(0x000fffffffffffff)),
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/*LowerCase=*/true);
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}
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// Use C99's hexadecimal floating-point representation.
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static const size_t BufBytes = 128;
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char Buf[BufBytes];
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auto Written = FP.convertToHexString(
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Buf, /*HexDigits=*/0, /*UpperCase=*/false, APFloat::rmNearestTiesToEven);
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(void)Written;
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assert(Written != 0);
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assert(Written < BufBytes);
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return Buf;
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}
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void WebAssemblyInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, bool IsVariadicDef) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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unsigned WAReg = Op.getReg();
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if (int(WAReg) >= 0)
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printRegName(O, WAReg);
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else if (OpNo >= Desc.getNumDefs() && !IsVariadicDef)
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O << "$pop" << WebAssemblyFunctionInfo::getWARegStackId(WAReg);
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else if (WAReg != WebAssemblyFunctionInfo::UnusedReg)
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O << "$push" << WebAssemblyFunctionInfo::getWARegStackId(WAReg);
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else
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O << "$drop";
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// Add a '=' suffix if this is a def.
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if (OpNo < MII.get(MI->getOpcode()).getNumDefs() || IsVariadicDef)
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O << '=';
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} else if (Op.isImm()) {
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O << Op.getImm();
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} else if (Op.isSFPImm()) {
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O << ::toString(APFloat(APFloat::IEEEsingle(), APInt(32, Op.getSFPImm())));
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} else if (Op.isDFPImm()) {
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O << ::toString(APFloat(APFloat::IEEEdouble(), APInt(64, Op.getDFPImm())));
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} else {
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assert(Op.isExpr() && "unknown operand kind in printOperand");
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// call_indirect instructions have a TYPEINDEX operand that we print
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// as a signature here, such that the assembler can recover this
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// information.
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auto SRE = static_cast<const MCSymbolRefExpr *>(Op.getExpr());
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if (SRE->getKind() == MCSymbolRefExpr::VK_WASM_TYPEINDEX) {
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auto &Sym = static_cast<const MCSymbolWasm &>(SRE->getSymbol());
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O << WebAssembly::signatureToString(Sym.getSignature());
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} else {
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Op.getExpr()->print(O, &MAI);
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}
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}
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}
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void WebAssemblyInstPrinter::printBrList(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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O << "{";
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for (unsigned I = OpNo, E = MI->getNumOperands(); I != E; ++I) {
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if (I != OpNo)
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O << ", ";
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O << MI->getOperand(I).getImm();
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}
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O << "}";
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}
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void WebAssemblyInstPrinter::printWebAssemblyP2AlignOperand(const MCInst *MI,
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unsigned OpNo,
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raw_ostream &O) {
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int64_t Imm = MI->getOperand(OpNo).getImm();
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if (Imm == WebAssembly::GetDefaultP2Align(MI->getOpcode()))
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return;
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O << ":p2align=" << Imm;
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}
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void WebAssemblyInstPrinter::printWebAssemblySignatureOperand(const MCInst *MI,
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unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm()) {
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auto Imm = static_cast<unsigned>(Op.getImm());
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if (Imm != wasm::WASM_TYPE_NORESULT)
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O << WebAssembly::anyTypeToString(Imm);
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} else {
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auto Expr = cast<MCSymbolRefExpr>(Op.getExpr());
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auto *Sym = cast<MCSymbolWasm>(&Expr->getSymbol());
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if (Sym->getSignature()) {
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O << WebAssembly::signatureToString(Sym->getSignature());
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} else {
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// Disassembler does not currently produce a signature
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O << "unknown_type";
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}
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}
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}
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