bcaf31ec3f
A target can return if a misaligned access is 'fast' as defined by the target or not. In reality there can be different levels of 'fast' and 'slow'. This patch changes the boolean 'Fast' argument of the allowsMisalignedMemoryAccesses family of functions to an unsigned representing its speed. A target can still define it as it wants and the direct translation of the current code uses 0 and 1 for current false and true. This makes the change an NFC. Subsequent patch will start using an actual value of speed in the load/store vectorizer to compare if a vectorized access going to be not just fast, but not slower than before. Differential Revision: https://reviews.llvm.org/D124217
162 lines
7.1 KiB
C++
162 lines
7.1 KiB
C++
//- WebAssemblyISelLowering.h - WebAssembly DAG Lowering Interface -*- C++ -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines the interfaces that WebAssembly uses to lower LLVM
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/// code into a selection DAG.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
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#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYISELLOWERING_H
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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namespace WebAssemblyISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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#define HANDLE_NODETYPE(NODE) NODE,
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#define HANDLE_MEM_NODETYPE(NODE)
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#include "WebAssemblyISD.def"
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FIRST_MEM_OPCODE = ISD::FIRST_TARGET_MEMORY_OPCODE,
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#undef HANDLE_NODETYPE
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#undef HANDLE_MEM_NODETYPE
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#define HANDLE_NODETYPE(NODE)
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#define HANDLE_MEM_NODETYPE(NODE) NODE,
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#include "WebAssemblyISD.def"
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#undef HANDLE_NODETYPE
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#undef HANDLE_MEM_NODETYPE
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};
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} // end namespace WebAssemblyISD
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class WebAssemblySubtarget;
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class WebAssemblyTargetLowering final : public TargetLowering {
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public:
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WebAssemblyTargetLowering(const TargetMachine &TM,
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const WebAssemblySubtarget &STI);
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MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const override;
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MVT getPointerMemTy(const DataLayout &DL, uint32_t AS = 0) const override;
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private:
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/// Keep a pointer to the WebAssemblySubtarget around so that we can make the
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/// right decision when generating code for different targets.
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const WebAssemblySubtarget *Subtarget;
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AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
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bool shouldScalarizeBinop(SDValue VecOp) const override;
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FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
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const TargetLibraryInfo *LibInfo) const override;
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MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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bool isCheapToSpeculateCttz(Type *Ty) const override;
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bool isCheapToSpeculateCtlz(Type *Ty) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace, Align Alignment,
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MachineMemOperand::Flags Flags,
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unsigned *Fast) const override;
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bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
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bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
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const APInt &DemandedElts,
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const SelectionDAG &DAG,
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unsigned Depth) const override;
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TargetLoweringBase::LegalizeTypeAction
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getPreferredVectorAction(MVT VT) const override;
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SDValue LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &dl,
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SelectionDAG &DAG) const override;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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const char *getClearCacheBuiltinName() const override {
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report_fatal_error("llvm.clear_cache is not supported on wasm");
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}
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bool
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shouldSimplifyDemandedVectorElts(SDValue Op,
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const TargetLoweringOpt &TLO) const override;
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// Custom lowering hooks.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCopyToReg(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerIntrinsic(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerAccessVectorElement(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLoad(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerStore(SDValue Op, SelectionDAG &DAG) const;
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// Helper for LoadLoad and LowerStore
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bool MatchTableForLowering(SelectionDAG &DAG, const SDLoc &DL,
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const SDValue &Base, GlobalAddressSDNode *&GA,
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SDValue &Idx) const;
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// Custom DAG combine hooks
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SDValue
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PerformDAGCombine(SDNode *N,
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TargetLowering::DAGCombinerInfo &DCI) const override;
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};
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namespace WebAssembly {
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo);
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} // end namespace WebAssembly
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} // end namespace llvm
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#endif
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